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target/riscv: Rename the H irqs to VS irqs

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Backports commit 205377f8940898e4c53d1b44350a3d4934a2da72 from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:09:02 -04:00 committed by Lioncash
parent 0198a09698
commit fa04e7ea45
2 changed files with 9 additions and 9 deletions
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6
qemu/target/riscv/cpu.c
View file

@ -72,14 +72,14 @@ const char * const riscv_excp_names[] = {
const char * const riscv_intr_names[] = {
"u_software",
"s_software",
"h_software",
"vs_software",
"m_software",
"u_timer",
"s_timer",
"h_timer",
"vs_timer",
"m_timer",
"u_external",
"s_external",
"vs_external",
"h_external",
"m_external",
"reserved",

12
qemu/target/riscv/cpu_bits.h
View file

@ -515,29 +515,29 @@
/* Interrupt causes */
#define IRQ_U_SOFT 0
#define IRQ_S_SOFT 1
#define IRQ_H_SOFT 2 /* reserved */
#define IRQ_VS_SOFT 2 /* reserved */
#define IRQ_M_SOFT 3
#define IRQ_U_TIMER 4
#define IRQ_S_TIMER 5
#define IRQ_H_TIMER 6 /* reserved */
#define IRQ_VS_TIMER 6 /* reserved */
#define IRQ_M_TIMER 7
#define IRQ_U_EXT 8
#define IRQ_S_EXT 9
#define IRQ_H_EXT 10 /* reserved */
#define IRQ_VS_EXT 10 /* reserved */
#define IRQ_M_EXT 11
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
#define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_HSIP (1 << IRQ_H_SOFT)
#define MIP_VSSIP (1 << IRQ_VS_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT)
#define MIP_UTIP (1 << IRQ_U_TIMER)
#define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_HTIP (1 << IRQ_H_TIMER)
#define MIP_VSTIP (1 << IRQ_VS_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER)
#define MIP_UEIP (1 << IRQ_U_EXT)
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_HEIP (1 << IRQ_H_EXT)
#define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
/* sip masks */