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target/riscv: vector floating-point merge instructions

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Backports 64ab5846974140118c64e4d94ff2696932a0a58b
This commit is contained in:
LIU Zhiwei 2021-03-07 11:58:37 -05:00 committed by Lioncash
parent f9c9716534
commit fabc8bab77
7 changed files with 79 additions and 0 deletions
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3
qemu/header_gen.py
View file

@ -7166,6 +7166,9 @@ riscv_symbols = (
'helper_vfclass_v_h',
'helper_vfclass_v_w',
'helper_vfclass_v_d',
'helper_vfmerge_vfm_h',
'helper_vfmerge_vfm_w',
'helper_vfmerge_vfm_d',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

3
qemu/riscv32.h
View file

@ -4602,6 +4602,9 @@
#define helper_vfclass_v_h helper_vfclass_v_h_riscv32
#define helper_vfclass_v_w helper_vfclass_v_w_riscv32
#define helper_vfclass_v_d helper_vfclass_v_d_riscv32
#define helper_vfmerge_vfm_h helper_vfmerge_vfm_h_riscv32
#define helper_vfmerge_vfm_w helper_vfmerge_vfm_w_riscv32
#define helper_vfmerge_vfm_d helper_vfmerge_vfm_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

3
qemu/riscv64.h
View file

@ -4602,6 +4602,9 @@
#define helper_vfclass_v_h helper_vfclass_v_h_riscv64
#define helper_vfclass_v_w helper_vfclass_v_w_riscv64
#define helper_vfclass_v_d helper_vfclass_v_d_riscv64
#define helper_vfmerge_vfm_h helper_vfmerge_vfm_h_riscv64
#define helper_vfmerge_vfm_w helper_vfmerge_vfm_w_riscv64
#define helper_vfmerge_vfm_d helper_vfmerge_vfm_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

4
qemu/target/riscv/helper.h
View file

@ -1003,3 +1003,7 @@ DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)

2
qemu/target/riscv/insn32.decode
View file

@ -515,6 +515,8 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

40
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2217,3 +2217,43 @@ GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
/* Vector Floating-Point Merge Instruction */
GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (vext_check_isa_ill(s) &&
vext_check_reg(s, a->rd, false) &&
(s->sew != 0)) {
if (s->vl_eq_vlmax) {
tcg_gen_gvec_dup_i64(tcg_ctx, s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), tcg_ctx->cpu_fpr_risc[a->rs1]);
} else {
TCGv_ptr dest;
TCGv_i32 desc;
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
static gen_helper_vmv_vx * const fns[3] = {
gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w,
gen_helper_vmv_v_x_d,
};
TCGLabel *over = gen_new_label(tcg_ctx);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over);
dest = tcg_temp_new_ptr(tcg_ctx);
desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(tcg_ctx, dest, tcg_ctx->cpu_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](tcg_ctx, dest, tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_env, desc);
tcg_temp_free_ptr(tcg_ctx, dest);
tcg_temp_free_i32(tcg_ctx, desc);
gen_set_label(tcg_ctx, over);
}
return true;
}
return false;
}

24
qemu/target/riscv/vector_helper.c
View file

@ -4170,3 +4170,27 @@ RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d_risc)
GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
/* Vector Floating-Point Merge Instruction */
#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
*((ETYPE *)vd + H(i)) \
= (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl)
GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)