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target/arm: Use unallocated_encoding for aarch32

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Promote this function from aarch64 to fully general use.
Use it to unify the code sequences for generating illegal
opcode exceptions.

Backports commit 3cb36637157088892e9e33ddb1034bffd1251d3b from qemu
This commit is contained in:
Richard Henderson 2019-11-18 20:09:21 -05:00 committed by Lioncash
parent d562bea784
commit fb2d3c9a9a
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
8 changed files with 18 additions and 21 deletions
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1
qemu/arm.h
View file

@ -3419,6 +3419,7 @@
#define sri_op sri_op_arm
#define sve_exception_el sve_exception_el_arm
#define sve_zcr_len_for_el sve_zcr_len_for_el_arm
#define unallocated_encoding unallocated_encoding_arm
#define uqadd_op uqadd_op_arm
#define uqsub_op uqsub_op_arm
#define usra_op usra_op_arm

1
qemu/armeb.h
View file

@ -3419,6 +3419,7 @@
#define sri_op sri_op_armeb
#define sve_exception_el sve_exception_el_armeb
#define sve_zcr_len_for_el sve_zcr_len_for_el_armeb
#define unallocated_encoding unallocated_encoding_armeb
#define uqadd_op uqadd_op_armeb
#define uqsub_op uqsub_op_armeb
#define usra_op usra_op_armeb

1
qemu/header_gen.py
View file

@ -3428,6 +3428,7 @@ arm_symbols = (
'sri_op',
'sve_exception_el',
'sve_zcr_len_for_el',
'unallocated_encoding',
'uqadd_op',
'uqsub_op',
'usra_op',

7
qemu/target/arm/translate-a64.c
View file

@ -480,13 +480,6 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
}
}
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
static void init_tmp_a64_array(DisasContext *s)
{
#ifdef CONFIG_DEBUG_TCG

2
qemu/target/arm/translate-a64.h
View file

@ -18,8 +18,6 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
void unallocated_encoding(DisasContext *s);
#define unsupported_encoding(s, insn) \
do { \
qemu_log_mask(LOG_UNIMP, \

3
qemu/target/arm/translate-vfp.inc.c
View file

@ -110,8 +110,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
unallocated_encoding(s);
return false;
}

22
qemu/target/arm/translate.c
View file

@ -1345,6 +1345,13 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
s->base.is_jmp = DISAS_NORETURN;
}
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
{
@ -1376,8 +1383,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
return;
}
gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
unallocated_encoding(s);
}
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
@ -7795,8 +7801,7 @@ static void gen_srs(DisasContext *s,
}
if (undef) {
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
unallocated_encoding(s);
return;
}
@ -9428,8 +9433,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
break;
default:
illegal_op:
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
unallocated_encoding(s);
break;
}
}
@ -11119,8 +11123,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
return;
illegal_op:
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
unallocated_encoding(s);
}
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
@ -11944,8 +11947,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
return;
illegal_op:
undef:
gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
unallocated_encoding(s);
}
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)

2
qemu/target/arm/translate.h
View file

@ -106,6 +106,8 @@ typedef struct DisasCompare {
bool value_global;
} DisasCompare;
void unallocated_encoding(DisasContext *s);
static inline int arm_dc_feature(DisasContext *dc, int feature)
{
return (dc->features & (1ULL << feature)) != 0;