mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-02-01 23:21:08 +00:00
tcg: Add opcodes for vector minmax arithmetic
Backports commit dd0a0fcdd8848c2a18970c44a62bd8f394c2b495 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
e0266239ea
commit
fb684825c8
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@ -1223,6 +1223,14 @@
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#define helper_gvec_shr16i helper_gvec_shr16i_aarch64
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#define helper_gvec_shr32i helper_gvec_shr32i_aarch64
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#define helper_gvec_shr64i helper_gvec_shr64i_aarch64
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#define helper_gvec_smax8 helper_gvec_smax8_aarch64
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#define helper_gvec_smax16 helper_gvec_smax16_aarch64
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#define helper_gvec_smax32 helper_gvec_smax32_aarch64
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#define helper_gvec_smax64 helper_gvec_smax64_aarch64
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#define helper_gvec_smin8 helper_gvec_smin8_aarch64
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#define helper_gvec_smin16 helper_gvec_smin16_aarch64
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#define helper_gvec_smin32 helper_gvec_smin32_aarch64
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#define helper_gvec_smin64 helper_gvec_smin64_aarch64
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#define helper_gvec_sub8 helper_gvec_sub8_aarch64
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#define helper_gvec_sub16 helper_gvec_sub16_aarch64
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#define helper_gvec_sub32 helper_gvec_sub32_aarch64
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@ -1243,6 +1251,14 @@
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#define helper_gvec_udot_h helper_gvec_udot_h_aarch64
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#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_aarch64
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#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_aarch64
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#define helper_gvec_umax8 helper_gvec_umax8_aarch64
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#define helper_gvec_umax16 helper_gvec_umax16_aarch64
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#define helper_gvec_umax32 helper_gvec_umax32_aarch64
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#define helper_gvec_umax64 helper_gvec_umax64_aarch64
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#define helper_gvec_umin8 helper_gvec_umin8_aarch64
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#define helper_gvec_umin16 helper_gvec_umin16_aarch64
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#define helper_gvec_umin32 helper_gvec_umin32_aarch64
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#define helper_gvec_umin64 helper_gvec_umin64_aarch64
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#define helper_gvec_usadd8 helper_gvec_usadd8_aarch64
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#define helper_gvec_usadd16 helper_gvec_usadd16_aarch64
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#define helper_gvec_usadd32 helper_gvec_usadd32_aarch64
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@ -2845,6 +2861,8 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64
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#define tcg_gen_gvec_smax tcg_gen_gvec_smax_aarch64
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#define tcg_gen_gvec_smin tcg_gen_gvec_smin_aarch64
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_aarch64
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_aarch64
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64
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@ -2853,6 +2871,8 @@
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#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_aarch64
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#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_aarch64
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#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_aarch64
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#define tcg_gen_gvec_umax tcg_gen_gvec_umax_aarch64
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#define tcg_gen_gvec_umin tcg_gen_gvec_umin_aarch64
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_aarch64
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_aarch64
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64
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@ -2971,8 +2991,10 @@
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#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64
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#define tcg_gen_smax_vec tcg_gen_smax_vec_aarch64
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#define tcg_gen_smin_i32 tcg_gen_smin_i32_aarch64
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#define tcg_gen_smin_i64 tcg_gen_smin_i64_aarch64
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#define tcg_gen_smin_vec tcg_gen_smin_vec_aarch64
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#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_aarch64
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#define tcg_gen_sssub_vec tcg_gen_sssub_vec_aarch64
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#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64
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@ -2990,8 +3012,10 @@
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#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
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#define tcg_gen_umax_i32 tcg_gen_umax_i32_aarch64
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#define tcg_gen_umax_i64 tcg_gen_umax_i64_aarch64
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#define tcg_gen_umax_vec tcg_gen_umax_vec_aarch64
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#define tcg_gen_umin_i32 tcg_gen_umin_i32_aarch64
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#define tcg_gen_umin_i64 tcg_gen_umin_i64_aarch64
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#define tcg_gen_umin_vec tcg_gen_umin_vec_aarch64
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#define tcg_gen_usadd_vec tcg_gen_usadd_vec_aarch64
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#define tcg_gen_ussub_vec tcg_gen_ussub_vec_aarch64
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#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64
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@ -1223,6 +1223,14 @@
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#define helper_gvec_shr16i helper_gvec_shr16i_aarch64eb
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#define helper_gvec_shr32i helper_gvec_shr32i_aarch64eb
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#define helper_gvec_shr64i helper_gvec_shr64i_aarch64eb
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#define helper_gvec_smax8 helper_gvec_smax8_aarch64eb
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#define helper_gvec_smax16 helper_gvec_smax16_aarch64eb
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#define helper_gvec_smax32 helper_gvec_smax32_aarch64eb
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#define helper_gvec_smax64 helper_gvec_smax64_aarch64eb
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#define helper_gvec_smin8 helper_gvec_smin8_aarch64eb
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#define helper_gvec_smin16 helper_gvec_smin16_aarch64eb
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#define helper_gvec_smin32 helper_gvec_smin32_aarch64eb
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#define helper_gvec_smin64 helper_gvec_smin64_aarch64eb
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#define helper_gvec_sub8 helper_gvec_sub8_aarch64eb
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#define helper_gvec_sub16 helper_gvec_sub16_aarch64eb
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#define helper_gvec_sub32 helper_gvec_sub32_aarch64eb
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@ -1243,6 +1251,14 @@
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#define helper_gvec_udot_h helper_gvec_udot_h_aarch64eb
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#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_aarch64eb
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#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_aarch64eb
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#define helper_gvec_umax8 helper_gvec_umax8_aarch64eb
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#define helper_gvec_umax16 helper_gvec_umax16_aarch64eb
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#define helper_gvec_umax32 helper_gvec_umax32_aarch64eb
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#define helper_gvec_umax64 helper_gvec_umax64_aarch64eb
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#define helper_gvec_umin8 helper_gvec_umin8_aarch64eb
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#define helper_gvec_umin16 helper_gvec_umin16_aarch64eb
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#define helper_gvec_umin32 helper_gvec_umin32_aarch64eb
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#define helper_gvec_umin64 helper_gvec_umin64_aarch64eb
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#define helper_gvec_usadd8 helper_gvec_usadd8_aarch64eb
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#define helper_gvec_usadd16 helper_gvec_usadd16_aarch64eb
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#define helper_gvec_usadd32 helper_gvec_usadd32_aarch64eb
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@ -2845,6 +2861,8 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64eb
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64eb
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64eb
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#define tcg_gen_gvec_smax tcg_gen_gvec_smax_aarch64eb
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#define tcg_gen_gvec_smin tcg_gen_gvec_smin_aarch64eb
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_aarch64eb
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_aarch64eb
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64eb
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@ -2853,6 +2871,8 @@
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#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_aarch64eb
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#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_aarch64eb
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#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_aarch64eb
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#define tcg_gen_gvec_umax tcg_gen_gvec_umax_aarch64eb
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#define tcg_gen_gvec_umin tcg_gen_gvec_umin_aarch64eb
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_aarch64eb
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_aarch64eb
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64eb
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@ -2971,8 +2991,10 @@
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#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64eb
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64eb
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#define tcg_gen_smax_vec tcg_gen_smax_vec_aarch64eb
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#define tcg_gen_smin_i32 tcg_gen_smin_i32_aarch64eb
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#define tcg_gen_smin_i64 tcg_gen_smin_i64_aarch64eb
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#define tcg_gen_smin_vec tcg_gen_smin_vec_aarch64eb
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#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_aarch64eb
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#define tcg_gen_sssub_vec tcg_gen_sssub_vec_aarch64eb
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#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb
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@ -2990,8 +3012,10 @@
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#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
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#define tcg_gen_umax_i32 tcg_gen_umax_i32_aarch64eb
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#define tcg_gen_umax_i64 tcg_gen_umax_i64_aarch64eb
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#define tcg_gen_umax_vec tcg_gen_umax_vec_aarch64eb
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#define tcg_gen_umin_i32 tcg_gen_umin_i32_aarch64eb
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#define tcg_gen_umin_i64 tcg_gen_umin_i64_aarch64eb
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#define tcg_gen_umin_vec tcg_gen_umin_vec_aarch64eb
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#define tcg_gen_usadd_vec tcg_gen_usadd_vec_aarch64eb
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#define tcg_gen_ussub_vec tcg_gen_ussub_vec_aarch64eb
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#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64eb
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@ -1028,3 +1028,227 @@ void HELPER(gvec_ussub64)(void *d, void *a, void *b, uint32_t desc)
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smin8)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int8_t)) {
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int8_t aa = *(int8_t *)(a + i);
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int8_t bb = *(int8_t *)(b + i);
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int8_t dd = aa < bb ? aa : bb;
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*(int8_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smin16)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int16_t)) {
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int16_t aa = *(int16_t *)(a + i);
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int16_t bb = *(int16_t *)(b + i);
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int16_t dd = aa < bb ? aa : bb;
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*(int16_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smin32)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int32_t)) {
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int32_t aa = *(int32_t *)(a + i);
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int32_t bb = *(int32_t *)(b + i);
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int32_t dd = aa < bb ? aa : bb;
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*(int32_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smin64)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int64_t)) {
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int64_t aa = *(int64_t *)(a + i);
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int64_t bb = *(int64_t *)(b + i);
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int64_t dd = aa < bb ? aa : bb;
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*(int64_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smax8)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int8_t)) {
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int8_t aa = *(int8_t *)(a + i);
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int8_t bb = *(int8_t *)(b + i);
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int8_t dd = aa > bb ? aa : bb;
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*(int8_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smax16)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int16_t)) {
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int16_t aa = *(int16_t *)(a + i);
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int16_t bb = *(int16_t *)(b + i);
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int16_t dd = aa > bb ? aa : bb;
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*(int16_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smax32)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int32_t)) {
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int32_t aa = *(int32_t *)(a + i);
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int32_t bb = *(int32_t *)(b + i);
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int32_t dd = aa > bb ? aa : bb;
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*(int32_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_smax64)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int64_t)) {
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int64_t aa = *(int64_t *)(a + i);
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int64_t bb = *(int64_t *)(b + i);
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int64_t dd = aa > bb ? aa : bb;
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*(int64_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_umin8)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
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uint8_t aa = *(uint8_t *)(a + i);
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uint8_t bb = *(uint8_t *)(b + i);
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uint8_t dd = aa < bb ? aa : bb;
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*(uint8_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_umin16)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
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uint16_t aa = *(uint16_t *)(a + i);
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uint16_t bb = *(uint16_t *)(b + i);
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uint16_t dd = aa < bb ? aa : bb;
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*(uint16_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_umin32)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
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uint32_t aa = *(uint32_t *)(a + i);
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uint32_t bb = *(uint32_t *)(b + i);
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uint32_t dd = aa < bb ? aa : bb;
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*(uint32_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_umin64)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
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uint64_t aa = *(uint64_t *)(a + i);
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uint64_t bb = *(uint64_t *)(b + i);
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uint64_t dd = aa < bb ? aa : bb;
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*(uint64_t *)(d + i) = dd;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_umax8)(void *d, void *a, void *b, uint32_t desc)
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{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
|
||||
uint8_t aa = *(uint8_t *)(a + i);
|
||||
uint8_t bb = *(uint8_t *)(b + i);
|
||||
uint8_t dd = aa > bb ? aa : bb;
|
||||
*(uint8_t *)(d + i) = dd;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_umax16)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
|
||||
uint16_t aa = *(uint16_t *)(a + i);
|
||||
uint16_t bb = *(uint16_t *)(b + i);
|
||||
uint16_t dd = aa > bb ? aa : bb;
|
||||
*(uint16_t *)(d + i) = dd;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_umax32)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
|
||||
uint32_t aa = *(uint32_t *)(a + i);
|
||||
uint32_t bb = *(uint32_t *)(b + i);
|
||||
uint32_t dd = aa > bb ? aa : bb;
|
||||
*(uint32_t *)(d + i) = dd;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_umax64)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
|
||||
uint64_t aa = *(uint64_t *)(a + i);
|
||||
uint64_t bb = *(uint64_t *)(b + i);
|
||||
uint64_t dd = aa > bb ? aa : bb;
|
||||
*(uint64_t *)(d + i) = dd;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -206,6 +206,26 @@ DEF_HELPER_FLAGS_4(gvec_ussub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
|||
DEF_HELPER_FLAGS_4(gvec_ussub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ussub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_smin8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_smin16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_smin32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_smin64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_smax8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_smax16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_smax32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_smax64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_umin8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_umin16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_umin32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_umin64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_umax8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_umax16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_umax32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_umax64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
|
|
|||
24
qemu/arm.h
24
qemu/arm.h
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_arm
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_arm
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_arm
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_arm
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_arm
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_arm
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_arm
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_arm
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_arm
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_arm
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_arm
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_arm
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_arm
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_arm
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_arm
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_arm
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_arm
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_arm
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_arm
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_arm
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_arm
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_arm
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_arm
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_arm
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_arm
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_arm
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_arm
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_arm
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_arm
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_arm
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_arm
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_arm
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_arm
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_arm
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_arm
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_arm
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_arm
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_arm
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_arm
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_arm
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_arm
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_arm
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_arm
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_arm
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_arm
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_arm
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_arm
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_arm
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_arm
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_arm
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_arm
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_arm
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_arm
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_arm
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_arm
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_arm
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_arm
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_arm
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_arm
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_arm
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_arm
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_arm
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_arm
|
||||
|
|
|
|||
24
qemu/armeb.h
24
qemu/armeb.h
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_armeb
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_armeb
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_armeb
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_armeb
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_armeb
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_armeb
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_armeb
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_armeb
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_armeb
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_armeb
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_armeb
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_armeb
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_armeb
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_armeb
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_armeb
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_armeb
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_armeb
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_armeb
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_armeb
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_armeb
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_armeb
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_armeb
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_armeb
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_armeb
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_armeb
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_armeb
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_armeb
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_armeb
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_armeb
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_armeb
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_armeb
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_armeb
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_armeb
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_armeb
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_armeb
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_armeb
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_armeb
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_armeb
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_armeb
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_armeb
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_armeb
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_armeb
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_armeb
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_armeb
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_armeb
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_armeb
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_armeb
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_armeb
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_armeb
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_armeb
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_armeb
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_armeb
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_armeb
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_armeb
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_armeb
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_armeb
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_armeb
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_armeb
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_armeb
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_armeb
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_armeb
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_armeb
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_armeb
|
||||
|
|
|
|||
|
|
@ -1229,6 +1229,14 @@ symbols = (
|
|||
'helper_gvec_shr16i',
|
||||
'helper_gvec_shr32i',
|
||||
'helper_gvec_shr64i',
|
||||
'helper_gvec_smax8',
|
||||
'helper_gvec_smax16',
|
||||
'helper_gvec_smax32',
|
||||
'helper_gvec_smax64',
|
||||
'helper_gvec_smin8',
|
||||
'helper_gvec_smin16',
|
||||
'helper_gvec_smin32',
|
||||
'helper_gvec_smin64',
|
||||
'helper_gvec_sub8',
|
||||
'helper_gvec_sub16',
|
||||
'helper_gvec_sub32',
|
||||
|
|
@ -1249,6 +1257,14 @@ symbols = (
|
|||
'helper_gvec_udot_h',
|
||||
'helper_gvec_udot_idx_b',
|
||||
'helper_gvec_udot_idx_h',
|
||||
'helper_gvec_umax8',
|
||||
'helper_gvec_umax16',
|
||||
'helper_gvec_umax32',
|
||||
'helper_gvec_umax64',
|
||||
'helper_gvec_umin8',
|
||||
'helper_gvec_umin16',
|
||||
'helper_gvec_umin32',
|
||||
'helper_gvec_umin64',
|
||||
'helper_gvec_usadd8',
|
||||
'helper_gvec_usadd16',
|
||||
'helper_gvec_usadd32',
|
||||
|
|
@ -2851,6 +2867,8 @@ symbols = (
|
|||
'tcg_gen_gvec_sari',
|
||||
'tcg_gen_gvec_shli',
|
||||
'tcg_gen_gvec_shri',
|
||||
'tcg_gen_gvec_smax',
|
||||
'tcg_gen_gvec_smin',
|
||||
'tcg_gen_gvec_ssadd',
|
||||
'tcg_gen_gvec_sssub',
|
||||
'tcg_gen_gvec_sub',
|
||||
|
|
@ -2859,6 +2877,8 @@ symbols = (
|
|||
'tcg_gen_gvec_subs16',
|
||||
'tcg_gen_gvec_subs32',
|
||||
'tcg_gen_gvec_subs64',
|
||||
'tcg_gen_gvec_umax',
|
||||
'tcg_gen_gvec_umin',
|
||||
'tcg_gen_gvec_usadd',
|
||||
'tcg_gen_gvec_ussub',
|
||||
'tcg_gen_gvec_xor',
|
||||
|
|
@ -2977,8 +2997,10 @@ symbols = (
|
|||
'tcg_gen_shri_vec',
|
||||
'tcg_gen_smax_i32',
|
||||
'tcg_gen_smax_i64',
|
||||
'tcg_gen_smax_vec',
|
||||
'tcg_gen_smin_i32',
|
||||
'tcg_gen_smin_i64',
|
||||
'tcg_gen_smin_vec',
|
||||
'tcg_gen_ssadd_vec',
|
||||
'tcg_gen_sssub_vec',
|
||||
'tcg_gen_st_i32',
|
||||
|
|
@ -2996,8 +3018,10 @@ symbols = (
|
|||
'tcg_gen_subi_i64',
|
||||
'tcg_gen_umax_i32',
|
||||
'tcg_gen_umax_i64',
|
||||
'tcg_gen_umax_vec',
|
||||
'tcg_gen_umin_i32',
|
||||
'tcg_gen_umin_i64',
|
||||
'tcg_gen_umin_vec',
|
||||
'tcg_gen_usadd_vec',
|
||||
'tcg_gen_ussub_vec',
|
||||
'tcg_gen_vec_add8_i64',
|
||||
|
|
|
|||
24
qemu/m68k.h
24
qemu/m68k.h
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_m68k
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_m68k
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_m68k
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_m68k
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_m68k
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_m68k
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_m68k
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_m68k
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_m68k
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_m68k
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_m68k
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_m68k
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_m68k
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_m68k
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_m68k
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_m68k
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_m68k
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_m68k
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_m68k
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_m68k
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_m68k
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_m68k
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_m68k
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_m68k
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_m68k
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_m68k
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_m68k
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_m68k
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_m68k
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_m68k
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_m68k
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_m68k
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_m68k
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_m68k
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_m68k
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_m68k
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_m68k
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_m68k
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_m68k
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_m68k
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_m68k
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_m68k
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_m68k
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_m68k
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_m68k
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_m68k
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_m68k
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_m68k
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_m68k
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_m68k
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_m68k
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_m68k
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_m68k
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_m68k
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_m68k
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_m68k
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_m68k
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_m68k
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_m68k
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_m68k
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_m68k
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_m68k
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_m68k
|
||||
|
|
|
|||
24
qemu/mips.h
24
qemu/mips.h
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_mips
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mips
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mips
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_mips
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_mips
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_mips
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_mips
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_mips
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_mips
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_mips
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_mips
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mips
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mips
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_mips
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_mips
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_mips
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_mips
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_mips
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_mips
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_mips
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_mips
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_mips
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_mips
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_mips
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_mips
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_mips
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_mips
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_mips
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_mips
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mips
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_mips
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_mips
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_mips
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_mips
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_mips
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mips
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mips
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_mips
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_mips
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_mips
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_mips
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mips
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_mips
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_mips
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_mips
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_mips
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips
|
||||
|
|
|
|||
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_mips64
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mips64
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mips64
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_mips64
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_mips64
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_mips64
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_mips64
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_mips64
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_mips64
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_mips64
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_mips64
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mips64
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mips64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips64
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_mips64
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_mips64
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_mips64
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_mips64
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_mips64
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_mips64
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_mips64
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_mips64
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_mips64
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_mips64
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_mips64
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_mips64
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_mips64
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_mips64
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_mips64
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_mips64
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips64
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mips64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_mips64
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_mips64
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_mips64
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_mips64
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_mips64
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mips64
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mips64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_mips64
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips64
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips64
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_mips64
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_mips64
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_mips64
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips64
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips64
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_mips64
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips64
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips64
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_mips64
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_mips64
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_mips64
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64
|
||||
|
|
|
|||
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_mips64el
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mips64el
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mips64el
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_mips64el
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_mips64el
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_mips64el
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_mips64el
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_mips64el
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_mips64el
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_mips64el
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_mips64el
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mips64el
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mips64el
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips64el
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_mips64el
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_mips64el
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_mips64el
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_mips64el
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_mips64el
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_mips64el
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_mips64el
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_mips64el
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_mips64el
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_mips64el
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_mips64el
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_mips64el
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_mips64el
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_mips64el
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64el
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64el
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64el
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_mips64el
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_mips64el
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips64el
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mips64el
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64el
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_mips64el
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_mips64el
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_mips64el
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_mips64el
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_mips64el
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mips64el
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mips64el
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64el
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64el
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64el
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_mips64el
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips64el
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips64el
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_mips64el
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_mips64el
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_mips64el
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64el
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips64el
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips64el
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_mips64el
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips64el
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips64el
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_mips64el
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_mips64el
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_mips64el
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64el
|
||||
|
|
|
|||
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_mipsel
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mipsel
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mipsel
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_mipsel
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_mipsel
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_mipsel
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_mipsel
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_mipsel
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_mipsel
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_mipsel
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_mipsel
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mipsel
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mipsel
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mipsel
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_mipsel
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_mipsel
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_mipsel
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_mipsel
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_mipsel
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_mipsel
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_mipsel
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_mipsel
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_mipsel
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_mipsel
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_mipsel
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_mipsel
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_mipsel
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_mipsel
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mipsel
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mipsel
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mipsel
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_mipsel
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_mipsel
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mipsel
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mipsel
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mipsel
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_mipsel
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_mipsel
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_mipsel
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_mipsel
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_mipsel
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mipsel
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mipsel
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mipsel
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mipsel
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mipsel
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_mipsel
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mipsel
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mipsel
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_mipsel
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_mipsel
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_mipsel
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mipsel
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mipsel
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mipsel
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_mipsel
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mipsel
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mipsel
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_mipsel
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_mipsel
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_mipsel
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mipsel
|
||||
|
|
|
|||
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_powerpc
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_powerpc
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_powerpc
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_powerpc
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_powerpc
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_powerpc
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_powerpc
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_powerpc
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_powerpc
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_powerpc
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_powerpc
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_powerpc
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_powerpc
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_powerpc
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_powerpc
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_powerpc
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_powerpc
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_powerpc
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_powerpc
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_powerpc
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_powerpc
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_powerpc
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_powerpc
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_powerpc
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_powerpc
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_powerpc
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_powerpc
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_powerpc
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_powerpc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_powerpc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_powerpc
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_powerpc
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_powerpc
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_powerpc
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_powerpc
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_powerpc
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_powerpc
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_powerpc
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_powerpc
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_powerpc
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_powerpc
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_powerpc
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_powerpc
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_powerpc
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_powerpc
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_powerpc
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_powerpc
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_powerpc
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_powerpc
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_powerpc
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_powerpc
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_powerpc
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_powerpc
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_powerpc
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_powerpc
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_powerpc
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_powerpc
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_powerpc
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_powerpc
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_powerpc
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_powerpc
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_powerpc
|
||||
|
|
|
|||
24
qemu/sparc.h
24
qemu/sparc.h
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_sparc
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_sparc
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_sparc
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_sparc
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_sparc
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_sparc
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_sparc
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_sparc
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_sparc
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_sparc
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_sparc
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_sparc
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_sparc
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_sparc
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_sparc
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_sparc
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_sparc
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_sparc
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_sparc
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_sparc
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_sparc
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_sparc
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_sparc
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_sparc
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_sparc
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_sparc
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_sparc
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_sparc
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_sparc
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_sparc
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_sparc
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_sparc
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_sparc
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_sparc
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_sparc
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_sparc
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_sparc
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_sparc
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_sparc
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_sparc
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_sparc
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_sparc
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_sparc
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_sparc
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_sparc
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_sparc
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_sparc
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_sparc
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_sparc
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_sparc
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_sparc
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_sparc
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_sparc
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc
|
||||
|
|
|
|||
|
|
@ -1223,6 +1223,14 @@
|
|||
#define helper_gvec_shr16i helper_gvec_shr16i_sparc64
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_sparc64
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_sparc64
|
||||
#define helper_gvec_smax8 helper_gvec_smax8_sparc64
|
||||
#define helper_gvec_smax16 helper_gvec_smax16_sparc64
|
||||
#define helper_gvec_smax32 helper_gvec_smax32_sparc64
|
||||
#define helper_gvec_smax64 helper_gvec_smax64_sparc64
|
||||
#define helper_gvec_smin8 helper_gvec_smin8_sparc64
|
||||
#define helper_gvec_smin16 helper_gvec_smin16_sparc64
|
||||
#define helper_gvec_smin32 helper_gvec_smin32_sparc64
|
||||
#define helper_gvec_smin64 helper_gvec_smin64_sparc64
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_sparc64
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_sparc64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_sparc64
|
||||
|
|
@ -1243,6 +1251,14 @@
|
|||
#define helper_gvec_udot_h helper_gvec_udot_h_sparc64
|
||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_sparc64
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_sparc64
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_sparc64
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_sparc64
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_sparc64
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_sparc64
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_sparc64
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_sparc64
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_sparc64
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_sparc64
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_sparc64
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_sparc64
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_sparc64
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc64
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_sparc64
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_sparc64
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_sparc64
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_sparc64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc64
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_sparc64
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_sparc64
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_sparc64
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_sparc64
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_sparc64
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_sparc64
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_sparc64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc64
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc64
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_sparc64
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_sparc64
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_sparc64
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_sparc64
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_sparc64
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_sparc64
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc64
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_sparc64
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_sparc64
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_sparc64
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_sparc64
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_sparc64
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_sparc64
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_sparc64
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_sparc64
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc64
|
||||
|
|
|
|||
|
|
@ -549,6 +549,16 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
|
|||
|
||||
Similarly, v0 = -v1.
|
||||
|
||||
* smin_vec:
|
||||
* umin_vec:
|
||||
|
||||
Similarly, v0 = MIN(v1, v2), for signed and unsigned element types.
|
||||
|
||||
* smax_vec:
|
||||
* umax_vec:
|
||||
|
||||
Similarly, v0 = MAX(v1, v2), for signed and unsigned element types.
|
||||
|
||||
* ssadd_vec:
|
||||
* sssub_vec:
|
||||
* usadd_vec:
|
||||
|
|
|
|||
|
|
@ -136,6 +136,7 @@ typedef enum {
|
|||
#define TCG_TARGET_HAS_cmp_vec 1
|
||||
#define TCG_TARGET_HAS_mul_vec 1
|
||||
#define TCG_TARGET_HAS_sat_vec 0
|
||||
#define TCG_TARGET_HAS_minmax_vec 0
|
||||
|
||||
#define TCG_TARGET_DEFAULT_MO (0)
|
||||
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
|
||||
|
|
|
|||
|
|
@ -219,6 +219,7 @@ extern bool have_avx2;
|
|||
#define TCG_TARGET_HAS_cmp_vec 1
|
||||
#define TCG_TARGET_HAS_mul_vec 1
|
||||
#define TCG_TARGET_HAS_sat_vec 0
|
||||
#define TCG_TARGET_HAS_minmax_vec 0
|
||||
|
||||
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
|
||||
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
|
||||
|
|
|
|||
|
|
@ -1811,6 +1811,114 @@ void tcg_gen_gvec_ussub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t ao
|
|||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_smin(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fniv = tcg_gen_smin_vec,
|
||||
.fno = gen_helper_gvec_smin8,
|
||||
.opc = INDEX_op_smin_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fniv = tcg_gen_smin_vec,
|
||||
.fno = gen_helper_gvec_smin16,
|
||||
.opc = INDEX_op_smin_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_smin_i32,
|
||||
.fniv = tcg_gen_smin_vec,
|
||||
.fno = gen_helper_gvec_smin32,
|
||||
.opc = INDEX_op_smin_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_smin_i64,
|
||||
.fniv = tcg_gen_smin_vec,
|
||||
.fno = gen_helper_gvec_smin64,
|
||||
.opc = INDEX_op_smin_vec,
|
||||
.vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_umin(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fniv = tcg_gen_umin_vec,
|
||||
.fno = gen_helper_gvec_umin8,
|
||||
.opc = INDEX_op_umin_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fniv = tcg_gen_umin_vec,
|
||||
.fno = gen_helper_gvec_umin16,
|
||||
.opc = INDEX_op_umin_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_umin_i32,
|
||||
.fniv = tcg_gen_umin_vec,
|
||||
.fno = gen_helper_gvec_umin32,
|
||||
.opc = INDEX_op_umin_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_umin_i64,
|
||||
.fniv = tcg_gen_umin_vec,
|
||||
.fno = gen_helper_gvec_umin64,
|
||||
.opc = INDEX_op_umin_vec,
|
||||
.vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_smax(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fniv = tcg_gen_smax_vec,
|
||||
.fno = gen_helper_gvec_smax8,
|
||||
.opc = INDEX_op_smax_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fniv = tcg_gen_smax_vec,
|
||||
.fno = gen_helper_gvec_smax16,
|
||||
.opc = INDEX_op_smax_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_smax_i32,
|
||||
.fniv = tcg_gen_smax_vec,
|
||||
.fno = gen_helper_gvec_smax32,
|
||||
.opc = INDEX_op_smax_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_smax_i64,
|
||||
.fniv = tcg_gen_smax_vec,
|
||||
.fno = gen_helper_gvec_smax64,
|
||||
.opc = INDEX_op_smax_vec,
|
||||
.vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_umax(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fniv = tcg_gen_umax_vec,
|
||||
.fno = gen_helper_gvec_umax8,
|
||||
.opc = INDEX_op_umax_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fniv = tcg_gen_umax_vec,
|
||||
.fno = gen_helper_gvec_umax16,
|
||||
.opc = INDEX_op_umax_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_umax_i32,
|
||||
.fniv = tcg_gen_umax_vec,
|
||||
.fno = gen_helper_gvec_umax32,
|
||||
.opc = INDEX_op_umax_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_umax_i64,
|
||||
.fniv = tcg_gen_umax_vec,
|
||||
.fno = gen_helper_gvec_umax64,
|
||||
.opc = INDEX_op_umax_vec,
|
||||
.vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
/* Perform a vector negation using normal negation and a mask.
|
||||
Compare gen_subv_mask above. */
|
||||
static void gen_negv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
|
||||
|
|
|
|||
|
|
@ -234,6 +234,16 @@ void tcg_gen_gvec_usadd(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t ao
|
|||
void tcg_gen_gvec_ussub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
/* Min/max. */
|
||||
void tcg_gen_gvec_smin(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_umin(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_smax(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_umax(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
void tcg_gen_gvec_and(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_or(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
|
|
|
|||
|
|
@ -434,3 +434,23 @@ void tcg_gen_ussub_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCG
|
|||
{
|
||||
do_op3(s, vece, r, a, b, INDEX_op_ussub_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_smin_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(s, vece, r, a, b, INDEX_op_smin_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_umin_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(s, vece, r, a, b, INDEX_op_umin_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_smax_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(s, vece, r, a, b, INDEX_op_smax_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_umax_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(s, vece, r, a, b, INDEX_op_umax_vec);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -975,10 +975,15 @@ void tcg_gen_nor_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_v
|
|||
void tcg_gen_eqv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_not_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a);
|
||||
void tcg_gen_neg_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a);
|
||||
void tcg_gen_ssadd_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_usadd_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_sssub_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_ussub_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_ssadd_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_usadd_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_sssub_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_ussub_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_smin_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_umin_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_smax_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
void tcg_gen_umax_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
|
||||
|
||||
|
||||
void tcg_gen_shli_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
void tcg_gen_shri_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
|
|
|
|||
|
|
@ -230,6 +230,10 @@ DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
|||
DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
||||
DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
||||
DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
||||
DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
||||
DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
||||
DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
||||
DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
||||
|
||||
DEF(and_vec, 1, 2, 0, IMPLVEC)
|
||||
DEF(or_vec, 1, 2, 0, IMPLVEC)
|
||||
|
|
|
|||
|
|
@ -1054,6 +1054,11 @@ bool tcg_op_supported(TCGOpcode op)
|
|||
case INDEX_op_sssub_vec:
|
||||
case INDEX_op_ussub_vec:
|
||||
return have_vec && TCG_TARGET_HAS_sat_vec;
|
||||
case INDEX_op_smin_vec:
|
||||
case INDEX_op_umin_vec:
|
||||
case INDEX_op_smax_vec:
|
||||
case INDEX_op_umax_vec:
|
||||
return have_vec && TCG_TARGET_HAS_minmax_vec;
|
||||
|
||||
default:
|
||||
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
|
||||
|
|
|
|||
|
|
@ -187,6 +187,7 @@ typedef uint64_t TCGRegSet;
|
|||
#define TCG_TARGET_HAS_shv_vec 0
|
||||
#define TCG_TARGET_HAS_mul_vec 0
|
||||
#define TCG_TARGET_HAS_sat_vec 0
|
||||
#define TCG_TARGET_HAS_minmax_vec 0
|
||||
#else
|
||||
#define TCG_TARGET_MAYBE_vec 1
|
||||
#endif
|
||||
|
|
@ -1154,7 +1155,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s)
|
|||
}
|
||||
|
||||
// UNICORN: Added
|
||||
#define TCG_OP_DEFS_TABLE_SIZE 175
|
||||
#define TCG_OP_DEFS_TABLE_SIZE 179
|
||||
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
|
||||
|
||||
typedef struct TCGTargetOpDef {
|
||||
|
|
|
|||
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@ -1223,6 +1223,14 @@
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#define helper_gvec_shr16i helper_gvec_shr16i_x86_64
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||||
#define helper_gvec_shr32i helper_gvec_shr32i_x86_64
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||||
#define helper_gvec_shr64i helper_gvec_shr64i_x86_64
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||||
#define helper_gvec_smax8 helper_gvec_smax8_x86_64
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||||
#define helper_gvec_smax16 helper_gvec_smax16_x86_64
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||||
#define helper_gvec_smax32 helper_gvec_smax32_x86_64
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||||
#define helper_gvec_smax64 helper_gvec_smax64_x86_64
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||||
#define helper_gvec_smin8 helper_gvec_smin8_x86_64
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||||
#define helper_gvec_smin16 helper_gvec_smin16_x86_64
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||||
#define helper_gvec_smin32 helper_gvec_smin32_x86_64
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||||
#define helper_gvec_smin64 helper_gvec_smin64_x86_64
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||||
#define helper_gvec_sub8 helper_gvec_sub8_x86_64
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_x86_64
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||||
#define helper_gvec_sub32 helper_gvec_sub32_x86_64
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||||
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|
@ -1243,6 +1251,14 @@
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|||
#define helper_gvec_udot_h helper_gvec_udot_h_x86_64
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||||
#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_x86_64
|
||||
#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_x86_64
|
||||
#define helper_gvec_umax8 helper_gvec_umax8_x86_64
|
||||
#define helper_gvec_umax16 helper_gvec_umax16_x86_64
|
||||
#define helper_gvec_umax32 helper_gvec_umax32_x86_64
|
||||
#define helper_gvec_umax64 helper_gvec_umax64_x86_64
|
||||
#define helper_gvec_umin8 helper_gvec_umin8_x86_64
|
||||
#define helper_gvec_umin16 helper_gvec_umin16_x86_64
|
||||
#define helper_gvec_umin32 helper_gvec_umin32_x86_64
|
||||
#define helper_gvec_umin64 helper_gvec_umin64_x86_64
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_x86_64
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_x86_64
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_x86_64
|
||||
|
|
@ -2845,6 +2861,8 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_x86_64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_x86_64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_x86_64
|
||||
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_x86_64
|
||||
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_x86_64
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_x86_64
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_x86_64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_x86_64
|
||||
|
|
@ -2853,6 +2871,8 @@
|
|||
#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_x86_64
|
||||
#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_x86_64
|
||||
#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_x86_64
|
||||
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_x86_64
|
||||
#define tcg_gen_gvec_umin tcg_gen_gvec_umin_x86_64
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_x86_64
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_x86_64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_x86_64
|
||||
|
|
@ -2971,8 +2991,10 @@
|
|||
#define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_x86_64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_x86_64
|
||||
#define tcg_gen_smax_vec tcg_gen_smax_vec_x86_64
|
||||
#define tcg_gen_smin_i32 tcg_gen_smin_i32_x86_64
|
||||
#define tcg_gen_smin_i64 tcg_gen_smin_i64_x86_64
|
||||
#define tcg_gen_smin_vec tcg_gen_smin_vec_x86_64
|
||||
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_x86_64
|
||||
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_x86_64
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_x86_64
|
||||
|
|
@ -2990,8 +3012,10 @@
|
|||
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
|
||||
#define tcg_gen_umax_i32 tcg_gen_umax_i32_x86_64
|
||||
#define tcg_gen_umax_i64 tcg_gen_umax_i64_x86_64
|
||||
#define tcg_gen_umax_vec tcg_gen_umax_vec_x86_64
|
||||
#define tcg_gen_umin_i32 tcg_gen_umin_i32_x86_64
|
||||
#define tcg_gen_umin_i64 tcg_gen_umin_i64_x86_64
|
||||
#define tcg_gen_umin_vec tcg_gen_umin_vec_x86_64
|
||||
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_x86_64
|
||||
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_x86_64
|
||||
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_x86_64
|
||||
|
|
|
|||
Loading…
Reference in a new issue