yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-05 14:55:46 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: add 64-bit S-EL2 to EL exception table

Browse source 
With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in
secure mode, though it can only be AArch64.

This patch adds the target EL for exceptions from 64-bit S-EL2.

It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure
mode. Those values were never used in practice as the effective value of
HCR was always 0 in secure mode.

Backports 6c85f906261226e87211506bd9f787fd48a09f17
This commit is contained in:
Rémi Denis-Courmont 2021-03-04 14:00:22 -05:00 committed by Lioncash
parent 159043008f
commit fbdcef3ca5
2 changed files with 13 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
qemu/target/arm/helper.c
View file

@ -1089,12 +1089,12 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
* trapping to EL2 or EL3 for other accesses. * trapping to EL2 or EL3 for other accesses.
*/ */
int el = arm_current_el(env); int el = arm_current_el(env);
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
return CP_ACCESS_TRAP; return CP_ACCESS_TRAP;
} }
if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) if (el < 2 && (mdcr_el2 & MDCR_TPM)) {
&& !arm_is_secure_below_el3(env)) {
return CP_ACCESS_TRAP_EL2; return CP_ACCESS_TRAP_EL2;
} }
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
@ -1173,7 +1173,8 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
bool enabled, prohibited, filtered; bool enabled, prohibited, filtered;
bool secure = arm_is_secure(env); bool secure = arm_is_secure(env);
int el = arm_current_el(env); int el = arm_current_el(env);
uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
if (!arm_feature(env, ARM_FEATURE_PMU)) { if (!arm_feature(env, ARM_FEATURE_PMU)) {
return false; return false;
@ -1183,13 +1184,13 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
(counter < hpmn || counter == 31)) { (counter < hpmn || counter == 31)) {
e = env->cp15.c9_pmcr & PMCRE; e = env->cp15.c9_pmcr & PMCRE;
} else { } else {
e = env->cp15.mdcr_el2 & MDCR_HPME; e = mdcr_el2 & MDCR_HPME;
} }
enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
if (!secure) { if (!secure) {
if (el == 2 && (counter < hpmn || counter == 31)) { if (el == 2 && (counter < hpmn || counter == 31)) {
prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; prohibited = mdcr_el2 & MDCR_HPMD;
} else { } else {
prohibited = false; prohibited = false;
} }
@ -8680,13 +8681,13 @@ static const int8_t target_el_table[2][2][2][2][2][4] = {
{{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
{/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
{{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
{/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
{{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
{/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
{{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
{/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
{{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
{/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
}; };
/* /*

4
qemu/target/arm/op_helper.c
View file

@ -665,10 +665,10 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
break; break;
case CP_ACCESS_TRAP_EL2: case CP_ACCESS_TRAP_EL2:
/* /*
* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is * Requesting a trap to EL2 when we're in EL3 is
* a bug in the access function. * a bug in the access function.
*/ */
assert(!arm_is_secure(env) && arm_current_el(env) != 3); assert(arm_current_el(env) != 3);
target_el = 2; target_el = 2;
break; break;
case CP_ACCESS_TRAP_EL3: case CP_ACCESS_TRAP_EL3: