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target-m68k: add/sub manage word and byte operands
Backports commit 8a370c6cb770b618f7eb66628116c25e84588df8 from qemu
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parent
bc27695926
commit
fc28e8127f
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@ -1936,40 +1936,48 @@ DISAS_INSN(jump)
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DISAS_INSN(addsubq)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv src1;
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TCGv src2;
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TCGv src;
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TCGv dest;
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int val;
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TCGv val;
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int imm;
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TCGv addr;
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int opsize;
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SRC_EA(env, src1, OS_LONG, 0, &addr);
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val = (insn >> 9) & 7;
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if (val == 0)
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val = 8;
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if ((insn & 070) == 010) {
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/* Operation on address register is always long. */
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opsize = OS_LONG;
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} else {
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opsize = insn_opsize(insn);
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}
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SRC_EA(env, src, opsize, 1, &addr);
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imm = (insn >> 9) & 7;
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if (imm == 0) {
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imm = 8;
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}
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val = tcg_const_i32(tcg_ctx, imm);
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dest = tcg_temp_new(tcg_ctx);
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tcg_gen_mov_i32(tcg_ctx, dest, src1);
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tcg_gen_mov_i32(tcg_ctx, dest, src);
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if ((insn & 0x38) == 0x08) {
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/* Don't update condition codes if the destination is an
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address register. */
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if (insn & 0x0100) {
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tcg_gen_subi_i32(tcg_ctx, dest, dest, val);
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tcg_gen_sub_i32(tcg_ctx, dest, dest, val);
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} else {
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tcg_gen_addi_i32(tcg_ctx, dest, dest, val);
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tcg_gen_add_i32(tcg_ctx, dest, dest, val);
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}
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} else {
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src2 = tcg_const_i32(tcg_ctx, val);
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if (insn & 0x0100) {
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2);
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tcg_gen_sub_i32(tcg_ctx, dest, dest, src2);
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set_cc_op(s, CC_OP_SUBL);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, val);
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tcg_gen_sub_i32(tcg_ctx, dest, dest, val);
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set_cc_op(s, CC_OP_SUBB + opsize);
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} else {
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tcg_gen_add_i32(tcg_ctx, dest, dest, src2);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2);
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set_cc_op(s, CC_OP_ADDL);
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tcg_gen_add_i32(tcg_ctx, dest, dest, val);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, val);
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set_cc_op(s, CC_OP_ADDB + opsize);
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}
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gen_update_cc_add(s, dest, src2, OS_LONG);
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gen_update_cc_add(s, dest, val, opsize);
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}
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DEST_EA(env, insn, OS_LONG, dest, &addr);
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DEST_EA(env, insn, opsize, dest, &addr);
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}
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DISAS_INSN(tpf)
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