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memory: replace cpu_physical_memory_reset_dirty() with test-and-clear
The cpu_physical_memory_reset_dirty() function is sometimes used together with cpu_physical_memory_get_dirty(). This is not atomic since two separate accesses to the dirty memory bitmap are made. Turn cpu_physical_memory_reset_dirty() and cpu_physical_memory_clear_dirty_range_type() into the atomic cpu_physical_memory_test_and_clear_dirty(). Backports commit 03eebc9e3246b9b3f5925aa41f7dfd7c1e467875 from qemu
This commit is contained in:
parent
18ccd4b5be
commit
fc7b95d06a
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_aarch64
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_aarch64
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_aarch64
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_aarch64
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_aarch64
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_aarch64
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_aarch64
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@ -2095,6 +2096,7 @@
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#define memory_region_set_readonly memory_region_set_readonly_aarch64
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#define memory_region_set_skip_dump memory_region_set_skip_dump_aarch64
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#define memory_region_size memory_region_size_aarch64
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_aarch64
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#define memory_region_to_address_space memory_region_to_address_space_aarch64
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#define memory_region_transaction_begin memory_region_transaction_begin_aarch64
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#define memory_region_transaction_commit memory_region_transaction_commit_aarch64
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_aarch64eb
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_aarch64eb
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_aarch64eb
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_aarch64eb
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_aarch64eb
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_aarch64eb
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_aarch64eb
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@ -2095,6 +2096,7 @@
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#define memory_region_set_readonly memory_region_set_readonly_aarch64eb
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#define memory_region_set_skip_dump memory_region_set_skip_dump_aarch64eb
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#define memory_region_size memory_region_size_aarch64eb
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_aarch64eb
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#define memory_region_to_address_space memory_region_to_address_space_aarch64eb
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#define memory_region_transaction_begin memory_region_transaction_begin_aarch64eb
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#define memory_region_transaction_commit memory_region_transaction_commit_aarch64eb
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_arm
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_arm
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_arm
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_arm
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_arm
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_arm
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_arm
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@ -2095,6 +2096,7 @@
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#define memory_region_set_readonly memory_region_set_readonly_arm
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#define memory_region_set_skip_dump memory_region_set_skip_dump_arm
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#define memory_region_size memory_region_size_arm
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_arm
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#define memory_region_to_address_space memory_region_to_address_space_arm
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#define memory_region_transaction_begin memory_region_transaction_begin_arm
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#define memory_region_transaction_commit memory_region_transaction_commit_arm
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_armeb
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_armeb
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_armeb
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_armeb
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_armeb
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_armeb
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_armeb
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@ -2095,6 +2096,7 @@
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#define memory_region_set_readonly memory_region_set_readonly_armeb
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#define memory_region_set_skip_dump memory_region_set_skip_dump_armeb
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#define memory_region_size memory_region_size_armeb
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_armeb
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#define memory_region_to_address_space memory_region_to_address_space_armeb
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#define memory_region_transaction_begin memory_region_transaction_begin_armeb
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#define memory_region_transaction_commit memory_region_transaction_commit_armeb
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@ -124,8 +124,8 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
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can be detected */
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void tlb_protect_code(struct uc_struct *uc, ram_addr_t ram_addr)
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{
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cpu_physical_memory_reset_dirty(uc, ram_addr, TARGET_PAGE_SIZE,
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DIRTY_MEMORY_CODE);
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cpu_physical_memory_test_and_clear_dirty(uc, ram_addr, TARGET_PAGE_SIZE,
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DIRTY_MEMORY_CODE);
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}
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/* update the TLB so that writes in physical page 'phys_addr' are no longer
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24
qemu/exec.c
24
qemu/exec.c
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@ -714,16 +714,28 @@ static void tlb_reset_dirty_range_all(struct uc_struct* uc,
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}
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/* Note: start and end must be within the same ram block. */
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void cpu_physical_memory_reset_dirty(struct uc_struct* uc,
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ram_addr_t start, ram_addr_t length, unsigned client)
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bool cpu_physical_memory_test_and_clear_dirty(struct uc_struct *uc,
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ram_addr_t start,
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ram_addr_t length,
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unsigned client)
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{
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if (length == 0)
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return;
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cpu_physical_memory_clear_dirty_range(uc, start, length, client);
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unsigned long end, page;
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bool dirty;
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if (tcg_enabled(uc)) {
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if (length == 0) {
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return false;
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}
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end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
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page = start >> TARGET_PAGE_BITS;
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dirty = bitmap_test_and_clear_atomic(uc->ram_list.dirty_memory[client],
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page, end - page);
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if (dirty && tcg_enabled(uc)) {
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tlb_reset_dirty_range_all(uc, start, length);
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}
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return dirty;
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}
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hwaddr memory_region_section_get_iotlb(CPUState *cpu,
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@ -302,6 +302,7 @@ symbols = (
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'cpu_physical_memory_rw',
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'cpu_physical_memory_set_dirty_flag',
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'cpu_physical_memory_set_dirty_range',
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'cpu_physical_memory_test_and_clear_dirty',
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'cpu_physical_memory_unmap',
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'cpu_physical_memory_write_rom',
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'cpu_physical_memory_write_rom_internal',
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@ -2101,6 +2102,7 @@ symbols = (
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'memory_region_set_readonly',
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'memory_region_set_skip_dump',
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'memory_region_size',
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'memory_region_test_and_clear_dirty',
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'memory_region_to_address_space',
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'memory_region_transaction_begin',
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'memory_region_transaction_commit',
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@ -559,6 +559,23 @@ int memory_region_get_fd(MemoryRegion *mr);
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*/
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void *memory_region_get_ram_ptr(MemoryRegion *mr);
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/**
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* memory_region_test_and_clear_dirty: Check whether a range of bytes is dirty
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* for a specified client. It clears them.
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*
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* Checks whether a range of bytes has been written to since the last
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* call to memory_region_reset_dirty() with the same @client. Dirty logging
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* must be enabled.
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*
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* @mr: the memory region being queried.
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* @addr: the address (relative to the start of the region) being queried.
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* @size: the size of the range being queried.
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* @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or
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* %DIRTY_MEMORY_VGA.
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*/
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bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
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hwaddr size, unsigned client);
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/**
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* memory_region_set_readonly: Turn a memory region read-only (or read-write)
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*
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@ -163,20 +163,17 @@ static inline void cpu_physical_memory_set_dirty_lebitmap(struct uc_struct *uc,
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}
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#endif /* not _WIN32 */
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bool cpu_physical_memory_test_and_clear_dirty(struct uc_struct *uc,
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ram_addr_t start,
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ram_addr_t length,
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unsigned client);
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static inline void cpu_physical_memory_clear_dirty_range(struct uc_struct *uc, ram_addr_t start,
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ram_addr_t length,
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unsigned client)
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{
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unsigned long end, page;
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assert(client < DIRTY_MEMORY_NUM);
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end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
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page = start >> TARGET_PAGE_BITS;
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bitmap_clear(uc->ram_list.dirty_memory[client], page, end - page);
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cpu_physical_memory_test_and_clear_dirty(uc, start, length, DIRTY_MEMORY_CODE);
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}
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void cpu_physical_memory_reset_dirty(struct uc_struct *uc,
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ram_addr_t start, ram_addr_t length, unsigned client);
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#endif
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#endif
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_m68k
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_m68k
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_m68k
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_m68k
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_m68k
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_m68k
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_m68k
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#define memory_region_set_readonly memory_region_set_readonly_m68k
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#define memory_region_set_skip_dump memory_region_set_skip_dump_m68k
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#define memory_region_size memory_region_size_m68k
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_m68k
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#define memory_region_to_address_space memory_region_to_address_space_m68k
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#define memory_region_transaction_begin memory_region_transaction_begin_m68k
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#define memory_region_transaction_commit memory_region_transaction_commit_m68k
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@ -1344,6 +1344,13 @@ void *memory_region_get_ram_ptr(MemoryRegion *mr)
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return qemu_get_ram_ptr(mr->uc, mr->ram_addr & TARGET_PAGE_MASK);
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}
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bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
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hwaddr size, unsigned client)
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{
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return cpu_physical_memory_test_and_clear_dirty(mr->uc, mr->ram_addr + addr,
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size, client);
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}
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static void memory_region_update_container_subregions(MemoryRegion *subregion)
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{
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hwaddr offset = subregion->addr;
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_mips
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_mips
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_mips
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_mips
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_mips
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_mips
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_mips
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#define memory_region_set_readonly memory_region_set_readonly_mips
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#define memory_region_set_skip_dump memory_region_set_skip_dump_mips
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#define memory_region_size memory_region_size_mips
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_mips
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#define memory_region_to_address_space memory_region_to_address_space_mips
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#define memory_region_transaction_begin memory_region_transaction_begin_mips
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#define memory_region_transaction_commit memory_region_transaction_commit_mips
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#define cpu_physical_memory_rw cpu_physical_memory_rw_mips64
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_mips64
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_mips64
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_mips64
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_mips64
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_mips64
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_mips64
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#define memory_region_set_readonly memory_region_set_readonly_mips64
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#define memory_region_set_skip_dump memory_region_set_skip_dump_mips64
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#define memory_region_size memory_region_size_mips64
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_mips64
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#define memory_region_to_address_space memory_region_to_address_space_mips64
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#define memory_region_transaction_begin memory_region_transaction_begin_mips64
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#define memory_region_transaction_commit memory_region_transaction_commit_mips64
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#define cpu_physical_memory_rw cpu_physical_memory_rw_mips64el
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_mips64el
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_mips64el
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_mips64el
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_mips64el
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_mips64el
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_mips64el
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#define memory_region_set_readonly memory_region_set_readonly_mips64el
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#define memory_region_set_skip_dump memory_region_set_skip_dump_mips64el
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#define memory_region_size memory_region_size_mips64el
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_mips64el
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#define memory_region_to_address_space memory_region_to_address_space_mips64el
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#define memory_region_transaction_begin memory_region_transaction_begin_mips64el
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#define memory_region_transaction_commit memory_region_transaction_commit_mips64el
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#define cpu_physical_memory_rw cpu_physical_memory_rw_mipsel
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_mipsel
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_mipsel
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_mipsel
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_mipsel
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_mipsel
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_mipsel
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#define memory_region_set_readonly memory_region_set_readonly_mipsel
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#define memory_region_set_skip_dump memory_region_set_skip_dump_mipsel
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#define memory_region_size memory_region_size_mipsel
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_mipsel
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#define memory_region_to_address_space memory_region_to_address_space_mipsel
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#define memory_region_transaction_begin memory_region_transaction_begin_mipsel
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#define memory_region_transaction_commit memory_region_transaction_commit_mipsel
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#define cpu_physical_memory_rw cpu_physical_memory_rw_powerpc
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_powerpc
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_powerpc
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_powerpc
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_powerpc
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_powerpc
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_powerpc
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#define memory_region_set_readonly memory_region_set_readonly_powerpc
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#define memory_region_set_skip_dump memory_region_set_skip_dump_powerpc
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#define memory_region_size memory_region_size_powerpc
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_powerpc
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#define memory_region_to_address_space memory_region_to_address_space_powerpc
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#define memory_region_transaction_begin memory_region_transaction_begin_powerpc
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#define memory_region_transaction_commit memory_region_transaction_commit_powerpc
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#define cpu_physical_memory_rw cpu_physical_memory_rw_sparc
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_sparc
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_sparc
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_sparc
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_sparc
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#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_sparc
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_sparc
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#define memory_region_set_readonly memory_region_set_readonly_sparc
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#define memory_region_set_skip_dump memory_region_set_skip_dump_sparc
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#define memory_region_size memory_region_size_sparc
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#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_sparc
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#define memory_region_to_address_space memory_region_to_address_space_sparc
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#define memory_region_transaction_begin memory_region_transaction_begin_sparc
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#define memory_region_transaction_commit memory_region_transaction_commit_sparc
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@ -296,6 +296,7 @@
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#define cpu_physical_memory_rw cpu_physical_memory_rw_sparc64
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#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_sparc64
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#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_sparc64
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||||
#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_sparc64
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||||
#define cpu_physical_memory_unmap cpu_physical_memory_unmap_sparc64
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||||
#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_sparc64
|
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#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_sparc64
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|
@ -2095,6 +2096,7 @@
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#define memory_region_set_readonly memory_region_set_readonly_sparc64
|
||||
#define memory_region_set_skip_dump memory_region_set_skip_dump_sparc64
|
||||
#define memory_region_size memory_region_size_sparc64
|
||||
#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_sparc64
|
||||
#define memory_region_to_address_space memory_region_to_address_space_sparc64
|
||||
#define memory_region_transaction_begin memory_region_transaction_begin_sparc64
|
||||
#define memory_region_transaction_commit memory_region_transaction_commit_sparc64
|
||||
|
|
|
@ -296,6 +296,7 @@
|
|||
#define cpu_physical_memory_rw cpu_physical_memory_rw_x86_64
|
||||
#define cpu_physical_memory_set_dirty_flag cpu_physical_memory_set_dirty_flag_x86_64
|
||||
#define cpu_physical_memory_set_dirty_range cpu_physical_memory_set_dirty_range_x86_64
|
||||
#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_x86_64
|
||||
#define cpu_physical_memory_unmap cpu_physical_memory_unmap_x86_64
|
||||
#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_x86_64
|
||||
#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_x86_64
|
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|
@ -2095,6 +2096,7 @@
|
|||
#define memory_region_set_readonly memory_region_set_readonly_x86_64
|
||||
#define memory_region_set_skip_dump memory_region_set_skip_dump_x86_64
|
||||
#define memory_region_size memory_region_size_x86_64
|
||||
#define memory_region_test_and_clear_dirty memory_region_test_and_clear_dirty_x86_64
|
||||
#define memory_region_to_address_space memory_region_to_address_space_x86_64
|
||||
#define memory_region_transaction_begin memory_region_transaction_begin_x86_64
|
||||
#define memory_region_transaction_commit memory_region_transaction_commit_x86_64
|
||||
|
|
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Reference in a new issue