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tcg: Remove tcg_regset_set32

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It's not even clear what the interface REG and VAL32 were supposed to mean.
All uses had REG = 0 and VAL32 was the bitset assigned to the destination.

Backports commit f46934df662182097dce07d57ec00f37e4d2abf1 from qemu
This commit is contained in:
Richard Henderson 2018-03-04 23:39:48 -05:00 committed by Lioncash
parent 9a9c2ede4a
commit fc8b4316a9
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
8 changed files with 102 additions and 111 deletions
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31
qemu/tcg/aarch64/tcg-target.inc.c
View file

@ -125,11 +125,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1); ct->u.regs = 0xffffffffu;
break; break;
case 'l': /* qemu_ld / qemu_st address, data_reg */ case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1); ct->u.regs = 0xffffffffu;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry, /* x0 and x1 will be overwritten when reading the tlb entry,
and x2, and x3 for helper args, better to avoid using them. */ and x2, and x3 for helper args, better to avoid using them. */
@ -1940,20 +1940,21 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
static void tcg_target_init(TCGContext *s) static void tcg_target_init(TCGContext *s)
{ {
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
tcg_regset_set32(s->tcg_target_call_clobber_regs, 0, s->tcg_target_call_clobber_regs = 0xfffffffu;
(1 << TCG_REG_X0) | (1 << TCG_REG_X1) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X19);
(1 << TCG_REG_X2) | (1 << TCG_REG_X3) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X20);
(1 << TCG_REG_X4) | (1 << TCG_REG_X5) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X21);
(1 << TCG_REG_X6) | (1 << TCG_REG_X7) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X22);
(1 << TCG_REG_X8) | (1 << TCG_REG_X9) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X23);
(1 << TCG_REG_X10) | (1 << TCG_REG_X11) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X24);
(1 << TCG_REG_X12) | (1 << TCG_REG_X13) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X25);
(1 << TCG_REG_X14) | (1 << TCG_REG_X15) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X26);
(1 << TCG_REG_X16) | (1 << TCG_REG_X17) | tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X27);
(1 << TCG_REG_X18) | (1 << TCG_REG_X30)); tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X28);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X29);
s->reserved_regs = 0; s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);

23
qemu/tcg/arm/tcg-target.inc.c
View file

@ -264,13 +264,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); ct->u.regs = 0xffff;
break; break;
/* qemu_ld address */ /* qemu_ld address */
case 'l': case 'l':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); ct->u.regs = 0xffff;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry, /* r0-r2,lr will be overwritten when reading the tlb entry,
so don't use these. */ so don't use these. */
@ -284,7 +284,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
/* qemu_st address & data */ /* qemu_st address & data */
case 's': case 's':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); ct->u.regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only) /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */ and r0-r1 doing the byte swapping, so don't use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
@ -2164,14 +2164,15 @@ static void tcg_target_init(TCGContext *s)
} }
} }
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_R0) | s->tcg_target_call_clobber_regs = 0;
(1 << TCG_REG_R1) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0);
(1 << TCG_REG_R2) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R1);
(1 << TCG_REG_R3) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2);
(1 << TCG_REG_R12) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R3);
(1 << TCG_REG_R14)); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R12);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R14);
s->reserved_regs = 0; s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);

26
qemu/tcg/i386/tcg-target.inc.c
View file

@ -210,23 +210,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break; break;
case 'q': case 'q':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
if (TCG_TARGET_REG_BITS == 64) { ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
tcg_regset_set32(ct->u.regs, 0, 0xffff);
} else {
tcg_regset_set32(ct->u.regs, 0, 0xf);
}
break; break;
case 'Q': case 'Q':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xf); ct->u.regs = 0xf;
break; break;
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
if (TCG_TARGET_REG_BITS == 64) { ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_set32(ct->u.regs, 0, 0xffff);
} else {
tcg_regset_set32(ct->u.regs, 0, 0xff);
}
break; break;
case 'W': case 'W':
/* With TZCNT/LZCNT, we can have operand-size as an input. */ /* With TZCNT/LZCNT, we can have operand-size as an input. */
@ -236,11 +228,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
/* qemu_ld/st address constraint */ /* qemu_ld/st address constraint */
case 'L': case 'L':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
if (TCG_TARGET_REG_BITS == 64) { ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_set32(ct->u.regs, 0, 0xffff);
} else {
tcg_regset_set32(ct->u.regs, 0, 0xff);
}
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
break; break;
@ -2770,10 +2758,10 @@ static void tcg_target_init(TCGContext *s)
#endif #endif
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
} else { } else {
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xff;
} }
s->tcg_target_call_clobber_regs = 0; s->tcg_target_call_clobber_regs = 0;

35
qemu/tcg/mips/tcg-target.inc.c
View file

@ -2626,23 +2626,24 @@ static void tcg_target_init(TCGContext *s)
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
} }
s->tcg_target_call_clobber_regs =
(1 << TCG_REG_V0) | s->tcg_target_call_clobber_regs = 0;
(1 << TCG_REG_V1) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_V0);
(1 << TCG_REG_A0) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_V1);
(1 << TCG_REG_A1) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A0);
(1 << TCG_REG_A2) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A1);
(1 << TCG_REG_A3) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A2);
(1 << TCG_REG_T0) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A3);
(1 << TCG_REG_T1) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T0);
(1 << TCG_REG_T2) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T1);
(1 << TCG_REG_T3) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T2);
(1 << TCG_REG_T4) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T3);
(1 << TCG_REG_T5) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T4);
(1 << TCG_REG_T6) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T5);
(1 << TCG_REG_T7) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T6);
(1 << TCG_REG_T8) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T7);
(1 << TCG_REG_T9); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T8);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T9);
s->reserved_regs = 0; s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */

37
qemu/tcg/ppc/tcg-target.inc.c
View file

@ -277,11 +277,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break; break;
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff); ct->u.regs = 0xffffffff;
break; break;
case 'L': /* qemu_ld constraint */ case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff); ct->u.regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
@ -290,7 +290,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break; break;
case 'S': /* qemu_st constraint */ case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff); ct->u.regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
@ -2718,21 +2718,22 @@ static void tcg_target_init(TCGContext *s)
} }
#endif #endif
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
tcg_regset_set32(s->tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_R0) | s->tcg_target_call_clobber_regs = 0;
(1 << TCG_REG_R2) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0);
(1 << TCG_REG_R3) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2);
(1 << TCG_REG_R4) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R3);
(1 << TCG_REG_R5) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R4);
(1 << TCG_REG_R6) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R5);
(1 << TCG_REG_R7) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R6);
(1 << TCG_REG_R8) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R7);
(1 << TCG_REG_R9) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R8);
(1 << TCG_REG_R10) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R9);
(1 << TCG_REG_R11) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R10);
(1 << TCG_REG_R12)); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R11);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R12);
s->reserved_regs = 0; s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */

14
qemu/tcg/s390/tcg-target.inc.c
View file

@ -408,14 +408,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'r': /* all registers */ case 'r': /* all registers */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffff); ct->u.regs = 0xffff;
break; break;
case 'L': /* qemu_ld/st constraint */ case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffff); ct->u.regs = 0xffff;
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
break; break;
case 'a': /* force R2 for division */ case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
@ -2652,8 +2652,8 @@ static void tcg_target_init(TCGContext *s)
{ {
query_s390_facilities(); query_s390_facilities();
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
s->tcg_target_call_clobber_regs = 0; s->tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0);

46
qemu/tcg/sparc/tcg-target.inc.c
View file

@ -346,16 +346,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff); ct->u.regs = 0xffffffff;
break; break;
case 'R': case 'R':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, ALL_64); ct->u.regs = ALL_64;
break; break;
case 'A': /* qemu_ld/st address constraint */ case 'A': /* qemu_ld/st address constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff);
reserve_helpers: reserve_helpers:
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
@ -363,11 +362,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break; break;
case 's': /* qemu_st data 32-bit constraint */ case 's': /* qemu_st data 32-bit constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff); ct->u.regs = 0xffffffff;
goto reserve_helpers; goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */ case 'S': /* qemu_st data 64-bit constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, ALL_64); ct->u.regs = ALL_64;
goto reserve_helpers; goto reserve_helpers;
case 'I': case 'I':
ct->ct |= TCG_CT_CONST_S11; ct->ct |= TCG_CT_CONST_S11;
@ -1755,24 +1754,25 @@ static void tcg_target_init(TCGContext *s)
} }
#endif #endif
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64); s->tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
tcg_regset_set32(s->tcg_target_call_clobber_regs, 0, s->tcg_target_call_clobber_regs = 0;
(1 << TCG_REG_G1) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G1);
(1 << TCG_REG_G2) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G2);
(1 << TCG_REG_G3) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G3);
(1 << TCG_REG_G4) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G4);
(1 << TCG_REG_G5) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G5);
(1 << TCG_REG_G6) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G6);
(1 << TCG_REG_G7) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G7);
(1 << TCG_REG_O0) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O0);
(1 << TCG_REG_O1) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O1);
(1 << TCG_REG_O2) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O2);
(1 << TCG_REG_O3) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O3);
(1 << TCG_REG_O4) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O4);
(1 << TCG_REG_O5) | tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O5);
(1 << TCG_REG_O7)); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O6);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O7);
s->reserved_regs = 0; s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */

1
qemu/tcg/tcg.h
View file

@ -189,7 +189,6 @@ typedef enum TCGOpcode {
NB_OPS, NB_OPS,
} TCGOpcode; } TCGOpcode;
#define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
#define tcg_regset_set_reg(d, r) (d) |= 1L << (r) #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
#define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)