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tcg/s390: Remove 'R' constraint

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Since R0 is reserved, we don't need a special case constraint.

Backports commit e45d4ef6e345831c8d67a5bffe0d057efc20f4ff from qemu
This commit is contained in:
Richard Henderson 2018-03-01 11:05:55 -05:00 committed by Lioncash
parent 7852cc600d
commit fcc05dc1ce
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 15 deletions
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25
qemu/tcg/s390/tcg-target.inc.c
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@ -383,11 +383,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffff);
break;
case 'R': /* not R0 */
ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
break;
case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffff);
@ -2232,12 +2227,12 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_neg_i32, { "r", "r" } },
{ INDEX_op_shl_i32, { "r", "0", "Ri" } },
{ INDEX_op_shr_i32, { "r", "0", "Ri" } },
{ INDEX_op_sar_i32, { "r", "0", "Ri" } },
{ INDEX_op_shl_i32, { "r", "0", "ri" } },
{ INDEX_op_shr_i32, { "r", "0", "ri" } },
{ INDEX_op_sar_i32, { "r", "0", "ri" } },
{ INDEX_op_rotl_i32, { "r", "r", "Ri" } },
{ INDEX_op_rotr_i32, { "r", "r", "Ri" } },
{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
{ INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext8u_i32, { "r", "r" } },
@ -2287,12 +2282,12 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_neg_i64, { "r", "r" } },
{ INDEX_op_shl_i64, { "r", "r", "Ri" } },
{ INDEX_op_shr_i64, { "r", "r", "Ri" } },
{ INDEX_op_sar_i64, { "r", "r", "Ri" } },
{ INDEX_op_shl_i64, { "r", "r", "ri" } },
{ INDEX_op_shr_i64, { "r", "r", "ri" } },
{ INDEX_op_sar_i64, { "r", "r", "ri" } },
{ INDEX_op_rotl_i64, { "r", "r", "Ri" } },
{ INDEX_op_rotr_i64, { "r", "r", "Ri" } },
{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
{ INDEX_op_ext8s_i64, { "r", "r" } },
{ INDEX_op_ext8u_i64, { "r", "r" } },