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tcg/aarch64: Implement tcg_out_dupm_vec
The LD1R instruction does all the work. Note that the only useful addressing mode is a base register with no offset. Backports commit f23e5e15edfd49d5dd72cab2ed2d85ac354b2eeb from qemu
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a6fd4e2345
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@ -381,6 +381,9 @@ typedef enum {
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I3207_BLR = 0xd63f0000,
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I3207_RET = 0xd65f0000,
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/* AdvSIMD load/store single structure. */
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I3303_LD1R = 0x0d40c000,
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/* Load literal for loading the address at pc-relative offset */
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I3305_LDR = 0x58000000,
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I3305_LDR_v64 = 0x5c000000,
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@ -563,7 +566,14 @@ static inline uint32_t tcg_in32(TCGContext *s)
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#define tcg_out_insn(S, FMT, OP, ...) \
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glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
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static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19, TCGReg rt)
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static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,
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TCGReg rt, TCGReg rn, unsigned size)
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{
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tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
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}
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static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
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int imm19, TCGReg rt)
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{
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tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
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}
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@ -822,7 +832,30 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
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static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg r, TCGReg base, intptr_t offset)
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{
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return false;
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TCGReg temp = TCG_REG_TMP;
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if (offset < -0xffffff || offset > 0xffffff) {
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tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);
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tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);
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base = temp;
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} else {
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AArch64Insn add_insn = I3401_ADDI;
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if (offset < 0) {
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add_insn = I3401_SUBI;
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offset = -offset;
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}
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if (offset & 0xfff000) {
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tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
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base = temp;
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}
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if (offset & 0xfff) {
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tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
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base = temp;
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}
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}
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tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);
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return true;
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}
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static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
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