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target/arm: Enable HCR_E2H for VHE
Backports commit 03c76131bc494366a4357a1d265c5eb5cc820754 from qemu
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@ -1309,13 +1309,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
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#define HCR_ATA (1ULL << 56)
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#define HCR_DCT (1ULL << 57)
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/*
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* When we actually implement ARMv8.1-VHE we should add HCR_E2H to
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* HCR_MASK and then clear it again if the feature bit is not set in
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* hcr_write().
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*/
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#define HCR_MASK ((1ULL << 34) - 1)
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#define SCR_NS (1U << 0)
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#define SCR_IRQ (1U << 1)
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#define SCR_FIQ (1U << 2)
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@ -4508,7 +4508,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
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static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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uint64_t valid_mask = HCR_MASK;
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/* Begin with bits defined in base ARMv8.0. */
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uint64_t valid_mask = MAKE_64BIT_MASK(0, 34);
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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valid_mask &= ~HCR_HCD;
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@ -4522,6 +4523,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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*/
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valid_mask &= ~HCR_TSC;
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}
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if (cpu_isar_feature(aa64_vh, cpu)) {
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valid_mask |= HCR_E2H;
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}
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if (cpu_isar_feature(aa64_lor, cpu)) {
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valid_mask |= HCR_TLOR;
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}
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