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https://github.com/yuzu-emu/unicorn.git
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target-mips: microMIPS32 R6 POOL32F instructions
Add new microMIPS32 Release 6 POOL32F instructions Backports commit 2a24a7badeb6ad3ba72e7984f299623035d564d6 from qemu
This commit is contained in:
Yongbok Kim
Lioncash
parent
f816d6c637
commit
fe7e49dc20
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@ -14300,6 +14300,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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goto pool32f_invalid;
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}
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break;
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case CMP_CONDN_S:
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check_insn(ctx, ISA_MIPS32R6);
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gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
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break;
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case CMP_CONDN_D:
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check_insn(ctx, ISA_MIPS32R6);
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gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
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break;
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case POOL32FXF:
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gen_pool32fxf(ctx, rt, rs);
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break;
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@ -14328,6 +14336,19 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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goto pool32f_invalid;
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}
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break;
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case MIN_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
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break;
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case FMT_SDPS_D:
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gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
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break;
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default:
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goto pool32f_invalid;
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}
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break;
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case 0x08:
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/* [LS][WDU]XC1 */
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switch ((ctx->opcode >> 6) & 0x7) {
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@ -14361,6 +14382,19 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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goto pool32f_invalid;
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}
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break;
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case MAX_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
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break;
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case FMT_SDPS_D:
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gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
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break;
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default:
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goto pool32f_invalid;
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}
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break;
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case 0x18:
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/* 3D insns */
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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@ -14409,11 +14443,25 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case 0x20:
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/* MOV[FT].fmt and PREFX */
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/* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
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cc = (ctx->opcode >> 13) & 0x7;
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fmt = (ctx->opcode >> 9) & 0x3;
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switch ((ctx->opcode >> 6) & 0x7) {
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case MOVF_FMT:
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case MOVF_FMT: /* RINT_FMT */
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if (ctx->insn_flags & ISA_MIPS32R6) {
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/* RINT_FMT */
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switch (fmt) {
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case FMT_SDPS_S:
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gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
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break;
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case FMT_SDPS_D:
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gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
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break;
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default:
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goto pool32f_invalid;
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}
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} else {
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/* MOVF_FMT */
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switch (fmt) {
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case FMT_SDPS_S:
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gen_movcf_s(ctx, rs, rt, cc, 0);
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@ -14428,8 +14476,23 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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default:
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goto pool32f_invalid;
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}
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}
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break;
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case MOVT_FMT:
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case MOVT_FMT: /* CLASS_FMT */
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if (ctx->insn_flags & ISA_MIPS32R6) {
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/* CLASS_FMT */
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switch (fmt) {
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case FMT_SDPS_S:
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gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
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break;
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case FMT_SDPS_D:
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gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
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break;
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default:
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goto pool32f_invalid;
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}
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} else {
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/* MOVT_FMT */
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switch (fmt) {
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case FMT_SDPS_S:
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gen_movcf_s(ctx, rs, rt, cc, 1);
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@ -14444,6 +14507,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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default:
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goto pool32f_invalid;
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}
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}
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break;
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case PREFX:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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@ -14467,6 +14531,32 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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default: \
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goto pool32f_invalid; \
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}
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case MINA_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
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break;
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case FMT_SDPS_D:
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gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
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break;
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default:
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goto pool32f_invalid;
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}
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break;
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case MAXA_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
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break;
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case FMT_SDPS_D:
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gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
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break;
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default:
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goto pool32f_invalid;
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}
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break;
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case 0x30:
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/* regular FP ops */
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switch ((ctx->opcode >> 6) & 0x3) {
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@ -14495,12 +14585,89 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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break;
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case 0x38:
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/* cmovs */
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switch ((ctx->opcode >> 6) & 0x3) {
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case MOVN_FMT:
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switch ((ctx->opcode >> 6) & 0x7) {
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case MOVN_FMT: /* SELNEZ_FMT */
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if (ctx->insn_flags & ISA_MIPS32R6) {
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/* SELNEZ_FMT */
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
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break;
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case FMT_SDPS_D:
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gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
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break;
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default:
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goto pool32f_invalid;
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}
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} else {
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/* MOVN_FMT */
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FINSN_3ARG_SDPS(MOVN);
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}
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break;
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case MOVN_FMT_04:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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FINSN_3ARG_SDPS(MOVN);
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break;
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case MOVZ_FMT:
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case MOVZ_FMT: /* SELEQZ_FMT */
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if (ctx->insn_flags & ISA_MIPS32R6) {
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/* SELEQZ_FMT */
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
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break;
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case FMT_SDPS_D:
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gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
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break;
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default:
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goto pool32f_invalid;
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}
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} else {
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/* MOVZ_FMT */
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FINSN_3ARG_SDPS(MOVZ);
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}
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break;
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case MOVZ_FMT_05:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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FINSN_3ARG_SDPS(MOVZ);
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break;
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case SEL_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
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break;
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case FMT_SDPS_D:
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gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
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break;
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default:
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goto pool32f_invalid;
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}
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break;
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case MADDF_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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mips32_op = OPC_MADDF_S;
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goto do_fpop;
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case FMT_SDPS_D:
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mips32_op = OPC_MADDF_D;
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goto do_fpop;
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default:
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goto pool32f_invalid;
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}
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break;
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case MSUBF_FMT:
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check_insn(ctx, ISA_MIPS32R6);
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switch ((ctx->opcode >> 9) & 0x3) {
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case FMT_SDPS_S:
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mips32_op = OPC_MSUBF_S;
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goto do_fpop;
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case FMT_SDPS_D:
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mips32_op = OPC_MSUBF_D;
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goto do_fpop;
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default:
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goto pool32f_invalid;
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}
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break;
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default:
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goto pool32f_invalid;
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