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target/arm: Make PRIMASK register banked for v8M

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Make the PRIMASK register banked if v8M security extensions are enabled.

Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to
be restricted).

Backports commit 6d8048341995b31a77dc2e0dcaaf4e3df0e3121a from qemu
This commit is contained in:
Peter Maydell 2018-03-04 20:55:48 -05:00 committed by Lioncash
parent c9a7aad4dc
commit ff3f7811ce
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 3 additions and 3 deletions
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2
qemu/target/arm/cpu.h
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@ -436,7 +436,7 @@ typedef struct CPUARMState {
uint32_t bfar; /* BusFault Address */
unsigned mpu_ctrl; /* MPU_CTRL */
int exception;
uint32_t primask;
uint32_t primask[2];
uint32_t faultmask;
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
} v7m;

4
qemu/target/arm/helper.c
View file

@ -8103,7 +8103,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
env->regs[13] : env->v7m.other_sp;
case 16: /* PRIMASK */
return env->v7m.primask;
return env->v7m.primask[env->v7m.secure];
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
return env->v7m.basepri[env->v7m.secure];
@ -8171,7 +8171,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
}
break;
case 16: /* PRIMASK */
env->v7m.primask = val & 1;
env->v7m.primask[env->v7m.secure] = val & 1;
break;
case 17: /* BASEPRI */
env->v7m.basepri[env->v7m.secure] = val & 0xff;