mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-25 01:35:39 +00:00
2b2f91f82c
The reset vector is set in the init function don't set it again in realize. Backports commit 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 from qemu
420 lines
12 KiB
C
420 lines
12 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qapi/error.h"
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#include "fpu/softfloat-helpers.h"
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#include "uc_priv.h"
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/* RISC-V CPU definitions */
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const char * const riscv_int_regnames[] = {
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"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
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"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
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"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
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"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
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};
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const char * const riscv_fpr_regnames[] = {
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"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
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"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
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"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
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"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
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};
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const char * const riscv_excp_names[] = {
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"misaligned_fetch",
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"fault_fetch",
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"illegal_instruction",
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"breakpoint",
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"misaligned_load",
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"fault_load",
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"misaligned_store",
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"fault_store",
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"user_ecall",
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"supervisor_ecall",
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"hypervisor_ecall",
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"machine_ecall",
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"exec_page_fault",
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"load_page_fault",
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"reserved",
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"store_page_fault",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"guest_exec_page_fault",
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"guest_load_page_fault",
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"reserved",
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"guest_store_page_fault"
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};
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const char * const riscv_intr_names[] = {
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"u_software",
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"s_software",
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"vs_software",
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"m_software",
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"u_timer",
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"s_timer",
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"vs_timer",
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"m_timer",
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"u_external",
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"vs_external",
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"h_external",
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"m_external",
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"reserved",
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"reserved",
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"reserved",
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"reserved"
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};
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static void set_misa(CPURISCVState *env, target_ulong misa)
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{
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env->misa_mask = env->misa = misa;
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}
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static void set_priv_version(CPURISCVState *env, int priv_ver)
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{
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env->priv_ver = priv_ver;
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}
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static void set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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static void set_resetvec(CPURISCVState *env, int resetvec)
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{
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#ifndef CONFIG_USER_ONLY
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env->resetvec = resetvec;
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#endif
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}
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static void riscv_any_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_11_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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#if defined(TARGET_RISCV32)
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static void riscv_base32_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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}
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static void rv32gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_MMU);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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static void rv32imcu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, 0x8090);
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}
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static void rv32imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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static void rv32imafcu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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#elif defined(TARGET_RISCV64)
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static void riscv_base64_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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}
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static void rv64gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_MMU);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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static void rv64imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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#endif
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static ObjectClass *riscv_cpu_class_by_name(struct uc_struct *uc, const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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char **cpuname;
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cpuname = g_strsplit(cpu_model, ",", 1);
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typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
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oc = object_class_by_name(uc, typename);
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g_strfreev(cpuname);
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g_free(typename);
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if (!oc || !object_class_dynamic_cast(uc, oc, TYPE_RISCV_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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// Unicorn: if'd out
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#if 0
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static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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int i;
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
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#ifndef CONFIG_USER_ONLY
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ",
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(target_ulong)atomic_read(&env->mip));
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
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cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
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#endif
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for (i = 0; i < 32; i++) {
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cpu_fprintf(f, " %s " TARGET_FMT_lx,
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riscv_int_regnames[i], env->gpr[i]);
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if ((i & 3) == 3) {
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cpu_fprintf(f, "\n");
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}
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}
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if (flags & CPU_DUMP_FPU) {
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for (i = 0; i < 32; i++) {
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cpu_fprintf(f, " %s %016" PRIx64,
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riscv_fpr_regnames[i], env->fpr[i]);
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if ((i & 3) == 3) {
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cpu_fprintf(f, "\n");
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}
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}
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}
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}
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#endif
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static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
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{
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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env->pc = value;
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}
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static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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env->pc = tb->pc;
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}
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static bool riscv_cpu_has_work(CPUState *cs)
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{
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#ifndef CONFIG_USER_ONLY
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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/*
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* Definition of the WFI instruction requires it to ignore the privilege
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* mode and delegation registers, but respect individual enables
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*/
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return (atomic_read(&env->mip) & env->mie) != 0;
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#else
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return true;
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#endif
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}
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void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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env->pc = data[0];
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}
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static void riscv_cpu_reset(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs->uc, cpu);
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CPURISCVState *env = &cpu->env;
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mcc->parent_reset(cs);
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#ifndef CONFIG_USER_ONLY
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env->priv = PRV_M;
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env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
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env->mcause = 0;
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env->pc = env->resetvec;
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#endif
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cs->exception_index = EXCP_NONE;
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env->load_res = -1;
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set_default_nan_mode(1, &env->fp_status);
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}
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// Unicorn: if'd out
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#if 0
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static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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{
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#if defined(TARGET_RISCV32)
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info->print_insn = print_insn_riscv32;
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#elif defined(TARGET_RISCV64)
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info->print_insn = print_insn_riscv64;
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#endif
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}
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#endif
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static int riscv_cpu_realize(struct uc_struct *uc, DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(uc, dev);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(uc, dev, errp);
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return 0;
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}
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static void riscv_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
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{
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CPUState *cs = CPU(obj);
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RISCVCPU *cpu = RISCV_CPU(uc, obj);
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cpu_set_cpustate_pointers(cpu);
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cpu_exec_init(cs, &error_abort, opaque);
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}
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static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
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{
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RISCVCPUClass *mcc = RISCV_CPU_CLASS(uc, oc);
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CPUClass *cc = CPU_CLASS(uc, oc);
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DeviceClass *dc = DEVICE_CLASS(uc, oc);
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mcc->parent_realize = dc->realize;
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dc->realize = riscv_cpu_realize;
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mcc->parent_reset = cc->reset;
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cc->reset = riscv_cpu_reset;
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cc->class_by_name = riscv_cpu_class_by_name;
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cc->has_work = riscv_cpu_has_work;
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cc->do_interrupt = riscv_cpu_do_interrupt;
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cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
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//cc->dump_state = riscv_cpu_dump_state;
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cc->set_pc = riscv_cpu_set_pc;
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cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
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//cc->gdb_read_register = riscv_cpu_gdb_read_register;
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//cc->gdb_write_register = riscv_cpu_gdb_write_register;
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//cc->gdb_num_core_regs = 65;
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//cc->gdb_stop_before_watchpoint = true;
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//cc->disas_set_info = riscv_cpu_disas_set_info;
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#ifndef CONFIG_USER_ONLY
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cc->do_unassigned_access = riscv_cpu_unassigned_access;
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cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
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cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
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#endif
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#ifdef CONFIG_TCG
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cc->tcg_initialize = riscv_translate_init;
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cc->tlb_fill = riscv_cpu_tlb_fill;
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#endif
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/* For now, mark unmigratable: */
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//cc->vmsd = &vmstate_riscv_cpu;
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}
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#define DEFINE_CPU(type_name, initfn) \
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{ \
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.name = type_name, \
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.parent = TYPE_RISCV_CPU, \
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.instance_init = initfn \
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}
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static const TypeInfo riscv_cpu_type_infos[] = {
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DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
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#if defined(TARGET_RISCV32)
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DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
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#elif defined(TARGET_RISCV64)
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DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
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#endif
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{ .name = NULL }
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};
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void riscv_cpu_register_types(void *opaque) {
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const TypeInfo* cpu_infos = riscv_cpu_type_infos;
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TypeInfo parent_type_info = {
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.name = TYPE_RISCV_CPU,
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.parent = TYPE_CPU,
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.instance_userdata = opaque,
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.instance_size = sizeof(RISCVCPU),
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.instance_init = riscv_cpu_init,
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.abstract = true,
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.class_size = sizeof(RISCVCPUClass),
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.class_init = riscv_cpu_class_init,
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};
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type_register(opaque, &parent_type_info);
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while (cpu_infos->name) {
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type_register(opaque, cpu_infos);
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++cpu_infos;
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}
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}
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