Peter Maydell 05d479a8c0 target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry ... In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR are zeroed for an exception taken to Non-secure state; for an exception taken to Secure state they become UNKNOWN, and we chose to leave them at their previous values. In v8.1M the behaviour is specified more tightly and these registers are always zeroed regardless of the security state that the exception targets (see rule R_KPZV). Implement this. Backports a59b1ed618415212c5f0f05abc1192e14ad5fdbb		2021-03-03 18:55:56 -05:00
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arm	target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry	2021-03-03 18:55:56 -05:00
i386	x86 tcg cpus: Fix Lesser GPL version number	2021-03-02 13:33:10 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00