Peter Maydell 0c06666800 target/arm: Implement SG instruction corner cases ... The common situation of the SG instruction is that it is executed from S&NSC memory by a CPU in NS state. That case is handled by v7m_handle_execute_nsc(). However the instruction also has defined behaviour in a couple of other cases: * SG instruction in NS memory (behaves as a NOP) * SG in S memory but CPU already secure (clears IT bits and does nothing else) * SG instruction in v8M without Security Extension (NOP) These can be implemented in translate.c. Backports commit 76eff04d166b8fe747adbe82de8b7e060e668ff9 from qemu		2018-03-05 03:47:20 -05:00
..
accel	target/arm: [tcg] Port to generic translation framework	2018-03-04 20:28:06 -05:00
crypto
default-configs
docs
fpu	softfloat: define floatx80_round()	2018-03-03 20:57:27 -05:00
hw	mips: replace cpu_mips_init() with cpu_generic_init()	2018-03-05 00:49:10 -05:00
include	exec-all: extract tb->tc_* into a separate struct tc_tb	2018-03-05 02:57:22 -05:00
qapi	qapi: add explicit null to string input and output visitors	2018-03-03 20:32:50 -05:00
qobject	qnum: add uint type	2018-03-03 18:37:56 -05:00
qom	qom/cpu: move cpu_model null check to cpu_class_by_name()	2018-03-05 02:02:29 -05:00
scripts	scripts: use build_ prefix for string not piped through cgen()	2018-03-03 22:11:28 -05:00
target	target/arm: Implement SG instruction corner cases	2018-03-05 03:47:20 -05:00
tcg	tcg/mips: delete commented out extern keyword	2018-03-05 03:24:25 -05:00
util	bitmap: provide to_le/from_le helpers	2018-03-05 01:11:13 -05:00
aarch64.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
aarch64eb.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
accel.c
arm.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
armeb.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
atomic_template.h
CODING_STYLE
configure	configure: Drop AIX host support	2018-03-04 21:32:40 -05:00
COPYING
COPYING.LIB
cpu-exec-common.c
cpu-exec.c	exec-all: extract tb->tc_* into a separate struct tc_tb	2018-03-05 02:57:22 -05:00
cpus.c
cputlb.c	cputlb: Support generating CPU exceptions on memory transaction failures	2018-03-04 13:14:50 -05:00
exec.c	memory: Open code FlatView rendering	2018-03-04 02:06:48 -05:00
gen_all_header.sh
glib_compat.c	qapi: Improve qobject input visitor error reporting	2018-03-02 12:05:53 -05:00
HACKING
header_gen.py	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
ioport.c
LICENSE
m68k.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
Makefile
Makefile.objs
Makefile.target	tcg: Add generic translation framework	2018-03-04 14:31:16 -05:00
memory.c	memory: avoid a name clash with access macro	2018-03-05 01:13:01 -05:00
memory_ldst.inc.c
memory_mapping.c
mips.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
mips64.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
mips64el.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
mipsel.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
powerpc.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
qapi-schema.json	qapi: Update scripts to commit 01b2ffcedd94ad7b42bc870e4c6936c87ad03429	2018-03-03 18:32:12 -05:00
qemu-timer.c
rules.mak
softmmu_template.h	cputlb: Support generating CPU exceptions on memory transaction failures	2018-03-04 13:14:50 -05:00
sparc.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
sparc64.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00
tcg-runtime.c	exec-all: extract tb->tc_* into a separate struct tc_tb	2018-03-05 02:57:22 -05:00
translate-all.c	exec-all: extract tb->tc_* into a separate struct tc_tb	2018-03-05 02:57:22 -05:00
translate-all.h
translate-common.c
unicorn_common.h
VERSION
vl.c	util: add cacheinfo	2018-03-03 16:58:28 -05:00
vl.h
x86_64.h	target/arm: Implement BLXNS	2018-03-05 03:31:59 -05:00