unicorn/qemu/target
Alex Bennée 0d6ed39333
target/arm: generate a custom MIDR for -cpu max
While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually exist in the reported CPU type.

Avoid this problem by synthesising our own MIDR value.

Backports commit 2bd5f41c00686a1f847a60824d0375f3df2c26bf from qemu
2019-11-18 16:42:51 -05:00
..
arm target/arm: generate a custom MIDR for -cpu max 2019-11-18 16:42:51 -05:00
i386 x86: setup FS & GS base 2019-08-08 20:26:45 -04:00
m68k m68k comments break patch submission due to being incorrectly formatted 2019-08-08 14:26:45 -04:00
mips Removed hardcoded CP0C3_ULRI (#1098) 2019-08-08 20:08:57 -04:00
riscv RISC-V: Clear load reservations on context switch and SC 2019-08-08 17:15:45 -04:00
sparc cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00