Liu Jingqi 10d7f18674 x86/cpu: Enable MOVDIR64B cpu feature ... MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Backports commit 1c65775ffc2dbd276a8bffe592feba0e186a151c from qemu		2018-12-18 03:48:19 -05:00
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arm	target/arm: fix smc incorrectly trapping to EL3 when secure is off	2018-11-23 18:57:23 -05:00
i386	x86/cpu: Enable MOVDIR64B cpu feature	2018-12-18 03:48:19 -05:00
m68k	m68k: Silence compiler warnings	2018-11-16 21:23:55 -05:00
mips	target/mips: Disable R5900 support	2018-11-23 18:55:12 -05:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00