James Hogan 152323fe35 target/mips: Add CP0_Ebase.WG (write gate) support ... Add support for the CP0_EBase.WG bit, which allows upper bits to be written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the CP0_Config5.CV bit to control whether the exception vector for Cache Error exceptions is forced into KSeg1. This is necessary on MIPS32 to support Segmentation Control and Enhanced Virtual Addressing (EVA) extensions (where KSeg1 addresses may not represent an unmapped uncached segment). It is also useful on MIPS64 to allow the exception base to reside in XKPhys, and possibly out of range of KSEG0 and KSEG1. Backports commit 74dbf824a1313b6064bbebb981a7440951d70896 from qemu		2018-03-03 23:55:09 -05:00
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arm	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
i386	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
m68k	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
mips	target/mips: Add CP0_Ebase.WG (write gate) support	2018-03-03 23:55:09 -05:00
sparc	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00