Richard Henderson 15b2850f4d target/arm: Swap argument order for VSHL during decode ... Rather than perform the argument swap during code generation, perform it during decode. This means it doesn't have to be special cased later, and we can share code with aarch64 code generation. Hopefully the decode comment addresses any confusion that might arise in between. Backports commit e9eee5316ffec5f37643de806b2e5577c5c189cf from qemu		2020-05-15 21:07:59 -04:00
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arm	target/arm: Swap argument order for VSHL during decode	2020-05-15 21:07:59 -04:00
i386	various: Remove suspicious '\' character outside of #define in C code	2020-04-30 07:31:45 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/mips: Fix loongson multimedia condition instructions	2020-04-30 07:14:10 -04:00
riscv	target/riscv: Add a sifive-e34 cpu type	2020-04-30 21:08:10 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00