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unicorn/qemu/target-mips
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Maciej W. Rozycki 15bfd1dde7
target-mips: Tighten ISA level checks 
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.

Backports commit d9224450208e0de62323b64ace91f98bc31d6e2c from qemu
2018-02-11 16:37:17 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c Fix for MIPS issue. (#733) 2017-01-23 12:39:34 +08:00
cpu.h target-mips: Tighten ISA level checks 2018-02-11 16:37:17 -05:00
dsp_helper.c Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
helper.c target-mips: Tighten ISA level checks 2018-02-11 16:37:17 -05:00
helper.h target-mips: Fix CP0.Config3.ISAOnExc write accesses 2018-02-11 16:24:19 -05:00
lmi_helper.c import 2015-08-21 15:04:50 +08:00
Makefile.objs import 2015-08-21 15:04:50 +08:00
mips-defs.h import 2015-08-21 15:04:50 +08:00
msa_helper.c Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
op_helper.c target-mips: Fix CP0.Config3.ISAOnExc write accesses 2018-02-11 16:24:19 -05:00
TODO import 2015-08-21 15:04:50 +08:00
translate.c target-mips: Tighten ISA level checks 2018-02-11 16:37:17 -05:00
translate_init.c target-mips: assorted formatting fixes 2018-02-11 16:01:23 -05:00
unicorn.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
unicorn.h armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00