Benjamin Herrenschmidt 1722be3e73 tlb: Add ifetch argument to cpu_mmu_index() ... This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Backports commit 97ed5ccdee95f0b98bedc601ff979e368583472c from qemu		2018-02-17 15:23:37 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	cpu: Change cpu_exec_init() arg to cpu, not env	2018-02-17 15:23:18 -05:00
cpu.h	tlb: Add ifetch argument to cpu_mmu_index()	2018-02-17 15:23:37 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: fix offset calculation for Interrupts	2018-02-17 15:23:23 -05:00
helper.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	target-mips: fix MIPS64R6-generic configuration	2018-02-17 15:23:21 -05:00
msa_helper.c	target-mips: fix to clear MSACSR.Cause	2018-02-17 15:23:22 -05:00
op_helper.c	tlb: Add ifetch argument to cpu_mmu_index()	2018-02-17 15:23:37 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: simplify LWL/LDL mask generation	2018-02-17 15:23:27 -05:00
translate_init.c	target-mips: update mips32r5-generic into P5600	2018-02-17 15:23:27 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00