Bastian Koppelmann 177726afb8 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists ... manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu		2019-03-19 05:17:54 -04:00
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trans_privileged.inc.c	target/riscv: Convert RV priv insns to decodetree	2019-03-19 04:40:24 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvc.inc.c	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-19 04:53:07 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
trans_rvm.inc.c	target/riscv: Convert RV32A insns to decodetree	2019-03-18 16:25:50 -04:00