Richard Henderson 1aed8cee64 target/arm: Fix sve_uzp_p vs odd vector lengths ... Missed out on compressing the second half of a predicate with length vl % 512 > 256. Adjust all of the x + (y << s) to x | (y << s) as a general style fix. Drop the extract64 because the input uint64_t are known to be already zero-extended from the current size of the predicate. Backports 226e6c046c0fce8da32575aad020ca56a5a8064d		2021-03-30 14:27:58 -04:00
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arm	target/arm: Fix sve_uzp_p vs odd vector lengths	2021-03-30 14:27:58 -04:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature	2021-03-12 14:55:43 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv/pmp: Raise exception if no PMP entry is configured	2021-03-08 15:39:55 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00