unicorn/qemu/target
Christophe Lyon 1df67780cd target/arm: Add support for cortex-m7 CPU
This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.

Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".

Backports commit cf7beda5072e106ddce875c1996446540c5fe239 from qemu
2020-01-07 17:52:27 -05:00
..
arm target/arm: Add support for cortex-m7 CPU 2020-01-07 17:52:27 -05:00
i386 tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
m68k tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
mips tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
riscv tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
sparc tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00