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https://github.com/yuzu-emu/unicorn.git
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299 lines
9 KiB
C
299 lines
9 KiB
C
/*
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* AArch64 SVE translation
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*
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* Copyright (c) 2018 Linaro, Ltd
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "tcg-op.h"
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#include "tcg-op-gvec.h"
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#include "arm_ldst.h"
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#include "translate.h"
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#include "internals.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "translate-a64.h"
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/*
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* Include the generated decoder.
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*/
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#include "decode-sve.inc.c"
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/*
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* Implement all of the translator functions referenced by the decoder.
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*/
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/* Return the offset info CPUARMState of the predicate vector register Pn.
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* Note for this purpose, FFR is P16.
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*/
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static inline int pred_full_reg_offset(DisasContext *s, int regno)
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{
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return offsetof(CPUARMState, vfp.pregs[regno]);
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}
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/* Return the byte size of the whole predicate register, VL / 64. */
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static inline int pred_full_reg_size(DisasContext *s)
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{
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return s->sve_len >> 3;
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}
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/* Invoke a vector expander on two Zregs. */
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static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
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int esz, int rd, int rn)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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gvec_fn(tcg_ctx, esz, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn), vsz, vsz);
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}
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return true;
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}
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/* Invoke a vector expander on three Zregs. */
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static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
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int esz, int rd, int rn, int rm)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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gvec_fn(tcg_ctx, esz, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn),
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vec_full_reg_offset(s, rm), vsz, vsz);
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}
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return true;
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}
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/* Invoke a vector move on two Zregs. */
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static bool do_mov_z(DisasContext *s, int rd, int rn)
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{
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return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
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}
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/* Set the cpu flags as per a return from an SVE helper. */
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static void do_pred_flags(DisasContext *s, TCGv_i32 t)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_NF, t);
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tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_ZF, t, 2);
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tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CF, t, 1);
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_VF, 0);
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}
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/* Subroutines computing the ARM PredTest psuedofunction. */
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static void do_predtest1(DisasContext *s, TCGv_i64 d, TCGv_i64 g)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 t = tcg_temp_new_i32(tcg_ctx);
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gen_helper_sve_predtest1(tcg_ctx, t, d, g);
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do_pred_flags(s, t);
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tcg_temp_free_i32(tcg_ctx, t);
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}
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static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_ptr dptr = tcg_temp_new_ptr(tcg_ctx);
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TCGv_ptr gptr = tcg_temp_new_ptr(tcg_ctx);
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TCGv_i32 t;
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tcg_gen_addi_ptr(tcg_ctx, dptr, tcg_ctx->cpu_env, dofs);
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tcg_gen_addi_ptr(tcg_ctx, gptr, tcg_ctx->cpu_env, gofs);
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t = tcg_const_i32(tcg_ctx, words);
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gen_helper_sve_predtest(tcg_ctx, t, dptr, gptr, t);
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tcg_temp_free_ptr(tcg_ctx, dptr);
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tcg_temp_free_ptr(tcg_ctx, gptr);
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do_pred_flags(s, t);
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tcg_temp_free_i32(tcg_ctx, t);
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}
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/*
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*** SVE Logical - Unpredicated Group
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*/
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static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
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}
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static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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if (a->rn == a->rm) { /* MOV */
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return do_mov_z(s, a->rd, a->rn);
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} else {
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return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
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}
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}
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static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
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}
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static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
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}
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/*
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*** SVE Predicate Misc Group
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*/
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static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int nofs = pred_full_reg_offset(s, a->rn);
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int gofs = pred_full_reg_offset(s, a->pg);
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int words = DIV_ROUND_UP(pred_full_reg_size(s), 8);
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if (words == 1) {
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TCGv_i64 pn = tcg_temp_new_i64(tcg_ctx);
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TCGv_i64 pg = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_ld_i64(tcg_ctx, pn, tcg_ctx->cpu_env, nofs);
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tcg_gen_ld_i64(tcg_ctx, pg, tcg_ctx->cpu_env, gofs);
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do_predtest1(s, pn, pg);
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tcg_temp_free_i64(tcg_ctx, pn);
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tcg_temp_free_i64(tcg_ctx, pg);
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} else {
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do_predtest(s, nofs, gofs, words);
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}
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}
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return true;
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}
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/*
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*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
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*/
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/* Subroutine loading a vector register at VOFS of LEN bytes.
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* The load should begin at the address Rn + IMM.
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*/
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static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
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int rn, int imm)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
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uint32_t len_remain = len % 8;
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uint32_t nparts = len / 8 + ctpop8(len_remain);
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int midx = get_mem_index(s);
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TCGv_i64 addr, t0, t1;
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addr = tcg_temp_new_i64(tcg_ctx);
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t0 = tcg_temp_new_i64(tcg_ctx);
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/* Note that unpredicated load/store of vector/predicate registers
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* are defined as a stream of bytes, which equates to little-endian
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* operations on larger quantities. There is no nice way to force
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* a little-endian load for aarch64_be-linux-user out of line.
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*
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* Attempt to keep code expansion to a minimum by limiting the
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* amount of unrolling done.
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*/
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if (nparts <= 4) {
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int i;
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for (i = 0; i < len_align; i += 8) {
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tcg_gen_addi_i64(tcg_ctx, addr, cpu_reg_sp(s, rn), imm + i);
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tcg_gen_qemu_ld_i64(s->uc, t0, addr, midx, MO_LEQ);
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tcg_gen_st_i64(tcg_ctx, t0, tcg_ctx->cpu_env, vofs + i);
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}
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} else {
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TCGLabel *loop = gen_new_label(tcg_ctx);
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TCGv_ptr tp, i = tcg_const_local_ptr(tcg_ctx, 0);
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gen_set_label(tcg_ctx, loop);
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/* Minimize the number of local temps that must be re-read from
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* the stack each iteration. Instead, re-compute values other
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* than the loop counter.
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*/
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tp = tcg_temp_new_ptr(tcg_ctx);
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tcg_gen_addi_ptr(tcg_ctx, tp, i, imm);
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tcg_gen_extu_ptr_i64(tcg_ctx, addr, tp);
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tcg_gen_add_i64(tcg_ctx, addr, addr, cpu_reg_sp(s, rn));
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tcg_gen_qemu_ld_i64(s->uc, t0, addr, midx, MO_LEQ);
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tcg_gen_add_ptr(tcg_ctx, tp, tcg_ctx->cpu_env, i);
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tcg_gen_addi_ptr(tcg_ctx, i, i, 8);
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tcg_gen_st_i64(tcg_ctx, t0, tp, vofs);
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tcg_temp_free_ptr(tcg_ctx, tp);
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tcg_gen_brcondi_ptr(tcg_ctx, TCG_COND_LTU, i, len_align, loop);
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tcg_temp_free_ptr(tcg_ctx, i);
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}
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/* Predicate register loads can be any multiple of 2.
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* Note that we still store the entire 64-bit unit into cpu_env.
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*/
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if (len_remain) {
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tcg_gen_addi_i64(tcg_ctx, addr, cpu_reg_sp(s, rn), imm + len_align);
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switch (len_remain) {
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case 2:
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case 4:
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case 8:
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tcg_gen_qemu_ld_i64(s->uc, t0, addr, midx, MO_LE | ctz32(len_remain));
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break;
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case 6:
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t1 = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_qemu_ld_i64(s->uc, t0, addr, midx, MO_LEUL);
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tcg_gen_addi_i64(tcg_ctx, addr, addr, 4);
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tcg_gen_qemu_ld_i64(s->uc, t1, addr, midx, MO_LEUW);
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tcg_gen_deposit_i64(tcg_ctx, t0, t0, t1, 32, 32);
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tcg_temp_free_i64(tcg_ctx, t1);
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break;
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default:
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g_assert_not_reached();
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}
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tcg_gen_st_i64(tcg_ctx, t0, tcg_ctx->cpu_env, vofs + len_align);
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}
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tcg_temp_free_i64(tcg_ctx, addr);
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tcg_temp_free_i64(tcg_ctx, t0);
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}
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static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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int size = vec_full_reg_size(s);
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int off = vec_full_reg_offset(s, a->rd);
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do_ldr(s, off, size, a->rn, a->imm * size);
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}
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return true;
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}
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static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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int size = pred_full_reg_size(s);
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int off = pred_full_reg_offset(s, a->rd);
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do_ldr(s, off, size, a->rn, a->imm * size);
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}
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return true;
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}
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