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46284f1a41
MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Backports commit 01bc435b44b8802cc4697faa07d908684afbce4e from qemu |
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cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
dsp_helper.c | ||
helper.c | ||
helper.h | ||
lmi_helper.c | ||
Makefile.objs | ||
mips-defs.h | ||
msa_helper.c | ||
op_helper.c | ||
TODO | ||
translate.c | ||
translate_init.c | ||
unicorn.c | ||
unicorn.h |