Michael Davidsaver 2769c6ada0 armv7m: Fix reads of CONTROL register bit 1 ... The v7m CONTROL register bit 1 is SPSEL, which indicates the stack being used. We were storing this information not in v7m.control but in the separate v7m.other_sp structure field. Unfortunately, the code handling reads of the CONTROL register didn't take account of this, and so if SPSEL was updated by an exception entry or exit then a subsequent guest read of CONTROL would get the wrong value. Using a separate structure field doesn't really gain us anything in efficiency, so drop this unnecessary complexity in favour of simply storing all the bits in v7m.control. This is a migration compatibility break for M profile CPUs only. Backports commit abc24d86cc0364f402e438fae3acb14289b40734 from qemu		2018-03-02 13:26:38 -05:00
..
arm	armv7m: Fix reads of CONTROL register bit 1	2018-03-02 13:26:38 -05:00
i386	i386: Change stepping of Haswell to non-blacklisted value	2018-03-02 12:53:11 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target-mips: Provide function to test if a CPU supports an ISA	2018-03-02 08:20:19 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00