unicorn/qemu/target
Peter Maydell 2c8a0fe0d7
nvic: Implement AIRCR changes for v8M
The Application Interrupt and Reset Control Register has some changes
for v8M:
 * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
   real state if the security extension is implemented and otherwise
   are constant
 * the PRIGROUP field is banked between security states
 * non-secure code can be blocked from using the SYSRESET bit
   to reset the system if SYSRESETREQS is set

Implement the new state and the changes to register read and write.
For the moment we ignore the effects of the secure PRIGROUP.
We will implement the effects of PRIS and BFHFNMIS later.

Backports register-related additions in commit 3b2e934463121f06d04e4d17658a9a7cdc3717b0 from qemu
2018-03-07 08:30:34 -05:00
..
arm nvic: Implement AIRCR changes for v8M 2018-03-07 08:30:34 -05:00
i386 accel/tcg: add size paremeter in tlb_fill() 2018-03-06 10:56:34 -05:00
m68k target/m68k: add HMP command "info tlb" 2018-03-06 11:23:10 -05:00
mips accel/tcg: add size paremeter in tlb_fill() 2018-03-06 10:56:34 -05:00
sparc accel/tcg: add size paremeter in tlb_fill() 2018-03-06 10:56:34 -05:00