Peter Maydell 2dae268fcb target/arm: Implement v8.1M NOCP handling ... From v8.1M, disabled-coprocessor handling changes slightly: * coprocessors 8, 9, 14 and 15 are also governed by the cp10 enable bit, like cp11 * an extra range of instruction patterns is considered to be inside the coprocessor space We previously marked these up with TODO comments; implement the correct behaviour. Unfortunately there is no ID register field which indicates this behaviour. We could in theory test an unrelated ID register which indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch >= 3 (low-overhead-loops), but it seems better to simply define a new ARM_FEATURE_V8_1M feature flag and use it for this and other new-in-v8.1M behaviour that isn't identifiable from the ID registers. Backports commit 5d2555a1fe7370feeb1efbbf276a653040910017		2021-03-01 20:16:09 -05:00
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arm	target/arm: Implement v8.1M NOCP handling	2021-03-01 20:16:09 -05:00
i386	i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not available	2021-03-01 19:04:03 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00