Michael Clark 2e0c040062 RISC-V: Allow interrupt controllers to claim interrupts ... We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu		2019-03-19 23:48:12 -04:00
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arm	target/arm: Check access permission to ADDVL/ADDPL/RDVL	2019-03-19 05:42:59 -04:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 23:48:12 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00