Peter Maydell 2e3bd010a8 target/arm: Implement CLRM instruction ... In v8.1M the new CLRM instruction allows zeroing an arbitrary set of the general-purpose registers and APSR. Implement this. The encoding is a subset of the LDMIA T2 encoding, using what would be Rn=0b1111 (which UNDEFs for LDMIA). Backports 6e21a013fbdf54960a079dccc90772bb622e28e8		2021-03-03 18:00:28 -05:00
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arm	target/arm: Implement CLRM instruction	2021-03-03 18:00:28 -05:00
i386	x86 tcg cpus: Fix Lesser GPL version number	2021-03-02 13:33:10 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00