unicorn/qemu/target
Peter Maydell 31013d5a8f target/arm: Fix SMLAD incorrect setting of Q bit
The SMLAD instruction is supposed to:
* signed multiply Rn[15:0] * Rm[15:0]
* signed multiply Rn[31:16] * Rm[31:16]
* perform a signed addition of the products and Ra
* set Rd to the low 32 bits of the theoretical
infinite-precision result
* set the Q flag if the sign-extension of Rd
would differ from the infinite-precision result
(ie on overflow)

Our current implementation doesn't quite do this, though: it performs
an addition of the products setting Q on overflow, and then it adds
Ra, again possibly setting Q. This sometimes incorrectly sets Q when
the architecturally mandated only-check-for-overflow-once algorithm
does not. For instance:
r1 = 0x80008000; r2 = 0x80008000; r3 = 0xffffffff
smlad r0, r1, r2, r3
This is (-32768 * -32768) + (-32768 * -32768) - 1

The products are both 0x4000_0000, so when added together as 32-bit
signed numbers they overflow (and QEMU sets Q), but because the
addition of Ra == -1 brings the total back down to 0x7fff_ffff
there is no overflow for the complete operation and setting Q is
incorrect.

Fix this edge case by resorting to 64-bit arithmetic for the
case where we need to add three values together.

Backports commit 5288145d716338ace0f83e3ff05c4d07715bb4f4
2021-03-01 19:58:39 -05:00
..
arm target/arm: Fix SMLAD incorrect setting of Q bit 2021-03-01 19:58:39 -05:00
i386 i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not available 2021-03-01 19:04:03 -05:00
m68k target/m68k: consolidate physical translation offset into get_physical_address() 2021-02-25 23:13:48 -05:00
mips target/mips: Support variable page size 2020-06-14 21:09:51 -04:00
riscv target/riscv: Set instance_align on RISCVCPU TypeInfo 2021-03-01 19:00:27 -05:00
sparc softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00