Peter Maydell 311b6fd74c target/arm: Correct store of FPSCR value via FPCXT_S ... In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register, but we got the write behaviour wrong. On read, this register reads bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't just write back those bits -- it writes a value to the whole FPSCR, whose upper 4 bits are zeroes. We also incorrectly implemented the write-to-FPSCR as a simple store to vfp.xregs; this skips the "update the softfloat flags" part of the vfp_set_fpscr helper so the value would read back correctly but not actually take effect. Fix both of these things by doing a complete write to the FPSCR using the helper function. Backports 7fbf95a037d79c5e923ffb51ac902dbe9599c87f		2021-03-03 19:57:56 -05:00
..
arm	target/arm: Correct store of FPSCR value via FPCXT_S	2021-03-03 19:57:56 -05:00
i386	target/i386: Check privilege level for protected mode 'int N' task gate	2021-03-03 19:32:10 -05:00
m68k	m68k: fix some comment spelling errors	2021-03-03 19:13:26 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00