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Richard Henderson 31837384b3 target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* 
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.

Backports commit 2859d7b590760283a7b5aef40b723e9dfd7c98ba from qemu
2020-03-21 14:20:31 -04:00
..
arm target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* 2020-03-21 14:20:31 -04:00
i386 target/i386: Add the 'model-id' for Skylake -v3 CPU models 2020-03-21 12:27:24 -04:00
m68k m68k: Fix regression causing Single-Step via GDB/RSP to not single step 2020-03-21 12:15:08 -04:00
mips target/arm: fix TCG leak for fcvt half->double 2020-03-21 13:14:47 -04:00
riscv target/riscv: update mstatus.SD when FS is set dirty 2020-03-21 12:22:56 -04:00
sparc target/sparc: sun4u Invert Endian TTE bit 2020-01-07 19:21:30 -05:00