unicorn/qemu/target
Alex Bennée 33eda0f5d4
arm/translate-a64: initial decode for simd_two_reg_misc_fp16
This actually covers two different sections of the encoding table:

Advanced SIMD scalar two-register miscellaneous FP16
Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Backports commit 5d432be6fd6efe37833ac82623c3abd35117b421 from qemu
2018-03-08 18:14:04 -05:00
..
arm arm/translate-a64: initial decode for simd_two_reg_misc_fp16 2018-03-08 18:14:04 -05:00
i386 target/*/cpu.h: remove softfloat.h 2018-03-08 09:58:47 -05:00
m68k target/*/cpu.h: remove softfloat.h 2018-03-08 09:58:47 -05:00
mips unicorn/mips: Lessen the amount of MIPS_CPU macro usage 2018-03-07 10:50:08 -05:00
sparc target/*/cpu.h: remove softfloat.h 2018-03-08 09:58:47 -05:00