Richard Henderson 33f5bdabb1 target/arm: Complete TBI clearing for user-only for SVE ... There are a number of paths by which the TBI is still intact for user-only in the SVE helpers. Because we currently always set TBI for user-only, we do not need to pass down the actual TBI setting from above, and we can remove the top byte in the inner-most primitives, so that none are forgotten. Moreover, this keeps the "dirty" pointer around at the higher levels, where we need it for any MTE checking. Since the normal case, especially for user-only, goes through RAM, this clearing merely adds two insns per page lookup, which will be completely in the noise. Backports commit c4af8ba19b9d22aac79cab679a20b159af9d6809 from qemu		2021-02-25 22:37:12 -05:00
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arm	target/arm: Complete TBI clearing for user-only for SVE	2021-02-25 22:37:12 -05:00
i386	target/i386: reimplement fpatan using floatx80 operations	2021-02-25 13:48:32 -05:00
m68k	softfloat: merge floatx80_mod and floatx80_rem	2021-02-25 13:34:05 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00