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Richard Henderson 36407da586 target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE 
When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.

Backports commit cb092fbbaeb7b4e91b3f9c53150c8160f91577c7 from qemu
2020-03-21 16:35:07 -04:00
..
arm target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE 2020-03-21 16:35:07 -04:00
i386 target/i386: Add the 'model-id' for Skylake -v3 CPU models 2020-03-21 12:27:24 -04:00
m68k m68k: Fix regression causing Single-Step via GDB/RSP to not single step 2020-03-21 12:15:08 -04:00
mips target/arm: fix TCG leak for fcvt half->double 2020-03-21 13:14:47 -04:00
riscv target/riscv: update mstatus.SD when FS is set dirty 2020-03-21 12:22:56 -04:00
sparc target/sparc: sun4u Invert Endian TTE bit 2020-01-07 19:21:30 -05:00