Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
..
arm	hw/arm/tosa: Enable all CPU features by using the max target for A-class CPUs	2018-09-02 16:19:28 -04:00
core	machine: use class base init generated name	2018-03-11 16:54:40 -04:00
i386	pc: use generic cpu_model parsing	2018-03-20 13:22:05 -04:00
intc	qemu-common: push cpu.h inclusion out of qemu-common.h	2018-02-24 01:50:56 -05:00
m68k	target/m68k: Fix initialization of m68k targets	2018-09-03 17:04:42 -04:00
mips	hw/mips/mips_r4k: Fix initialization of MIPS target CPUs	2018-09-03 17:40:08 -04:00
riscv	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
sparc	target/sparc: Fix SPARC target initialization	2018-09-03 17:26:00 -04:00
sparc64	target/sparc: Fix SPARC target initialization	2018-09-03 17:26:00 -04:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00