Aurelien Jarno 3cc6b5251e target-mips: fix page fault address for LWL/LWR/LDL/LDR ... When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU currently reports the aligned address in CP0 BadVAddr, while the Windows NT kernel expects the unaligned address. This patch adds a byte access with the unaligned address at the beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page fault and fill the QEMU TLB. Backports commit 908680c6441ac468f4871d513f42be396ea0d264 from qemu		2018-02-17 15:23:22 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	cpu: Change cpu_exec_init() arg to cpu, not env	2018-02-17 15:23:18 -05:00
cpu.h	cpu-exec: Purge all uses of ENV_GET_CPU()	2018-02-17 15:23:18 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: remove excp_names[] from linux-user as it is unused	2018-02-11 17:05:40 -05:00
helper.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	target-mips: fix MIPS64R6-generic configuration	2018-02-17 15:23:21 -05:00
msa_helper.c	target-mips: fix to clear MSACSR.Cause	2018-02-17 15:23:22 -05:00
op_helper.c	target-mips: correct DERET instruction	2018-02-17 15:23:22 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: fix page fault address for LWL/LWR/LDL/LDR	2018-02-17 15:23:22 -05:00
translate_init.c	target-mips: fix MIPS64R6-generic configuration	2018-02-17 15:23:21 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00