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41c4efdb22
Do not yet convert the helpers to loop over opr_sz, but the descriptor allows the vector tail to be cleared. Which fixes an existing bug vs SVE. Backports commit effa992f153f5e7ab97ab843b565690748c5b402 from qemu
202 lines
9.6 KiB
Plaintext
202 lines
9.6 KiB
Plaintext
# AArch32 Neon data-processing instruction descriptions
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#
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# Copyright (c) 2020 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# VFP/Neon register fields; same as vfp.decode
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%vm_dp 5:1 0:4
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%vn_dp 7:1 16:4
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%vd_dp 22:1 12:4
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# Encodings for Neon data processing instructions where the T32 encoding
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# is a simple transformation of the A32 encoding.
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# More specifically, this file covers instructions where the A32 encoding is
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# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# and the T32 encoding is
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# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# This file works on the A32 encoding only; calling code for T32 has to
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# transform the insn into the A32 version first.
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######################################################################
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# 3-reg-same grouping:
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# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
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######################################################################
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&3same vm vn vd q size
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@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
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# For FP insns the high bit of 'size' is used as part of opcode decode
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@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
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VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
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VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
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VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
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VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
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VRHADD_S_3s 1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
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VRHADD_U_3s 1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
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@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
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VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
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VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
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VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
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VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
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VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
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VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
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VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
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VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
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VHSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
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VHSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
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VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
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VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
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VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
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VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
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VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
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VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
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# The _rev suffix indicates that Vn and Vm are reversed. This is
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# the case for shifts. In the Arm ARM these insns are documented
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# with the Vm and Vn fields in their usual places, but in the
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# assembly the operands are listed "backwards", ie in the order
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# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
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# to consider Vm and Vn as being in different fields in the insn,
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# which allows us to avoid special-casing shifts in the trans_
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# function code. We would otherwise need to manually swap the operands
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# over to call Neon helper functions that are shared with AArch64,
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# which does not have this odd reversed-operand situation.
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@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
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&3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
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VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
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VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
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# Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
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# The _rev suffix indicates that Vn and Vm are reversed (as explained
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# by the comment for the @3same_rev format).
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@3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \
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&3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
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{
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VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
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VQSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
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}
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{
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VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
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VQSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
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}
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{
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VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
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VRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
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}
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{
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VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
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VRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
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}
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{
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VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
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VQRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
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}
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{
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VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
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VQRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
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}
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VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
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VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
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VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
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VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
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VABD_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
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VABD_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
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VABA_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
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VABA_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
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VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
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VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
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VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
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VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
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VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
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VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
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VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
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VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
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VPMAX_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
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VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
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VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
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VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
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VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
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VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
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VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
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VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
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@3same_crypto .... .... .... .... .... .... .... .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
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SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp
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SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
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VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
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VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
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VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
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VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
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VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
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VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
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VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
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VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
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VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
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VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
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VCEQ_fp_3s 1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
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VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
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VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
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VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
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VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
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VMAX_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
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VMIN_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
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VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
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VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
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VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
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VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
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VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
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VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
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