Maciej W. Rozycki 45c45541d0 target-mips: Correct the writes to Status and Cause registers via gdbstub ... Make writes to CP0.Status and CP0.Cause have the same effect as executing corresponding MTC0 instructions would in Kernel Mode. Also ignore writes in the user emulation mode. Currently for requests from the GDB stub we write all the bits across both registers, ignoring any read-only locations, and do not synchronise the environment to evaluate side effects. We also write these registers in the user emulation mode even though a real kernel presents them as read only. Backports commit 81a423e6c6d3ccaa79de4e58024369c660c1eeb4 from qemu		2018-02-11 16:16:16 -05:00
..
cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
cpu.h	target-mips: Correct the writes to Status and Cause registers via gdbstub	2018-02-11 16:16:16 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: Use CPU_LOG_INT for logging related to interrupts	2018-02-10 21:12:41 -05:00
helper.h	rework code/block tracing	2016-01-22 18:42:27 -08:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	import	2015-08-21 15:04:50 +08:00
msa_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
op_helper.c	target-mips: Correct the writes to Status and Cause registers via gdbstub	2018-02-11 16:16:16 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: Correct MIPS16/microMIPS branch size calculation	2018-02-11 16:09:33 -05:00
translate_init.c	target-mips: assorted formatting fixes	2018-02-11 16:01:23 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00