Konrad Rzeszutek Wilk 475062aca9 i386: Define AMD's no SSB mitigation needed. ... AMD future CPUs expose a mechanism to tell the guest that the Speculative Store Bypass Disable is not needed and that the CPU is all good. This is exposed via the CPUID 8000_0008.EBX[26] bit. See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Backports commit 254790a909a2f153d689bfa7d8e8f0386cda870d from qemu		2018-07-03 00:24:58 -04:00
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arm	target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline	2018-06-29 14:15:33 -05:00
i386	i386: Define AMD's no SSB mitigation needed.	2018-07-03 00:24:58 -04:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-15 11:40:18 -04:00
mips	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00
sparc	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00