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unicorn/qemu/target
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Leon Alrae 4a1ec3bb80
target-mips: apply CP0.PageMask before writing into TLB entry 
PFN0 and PFN1 have to be masked out with PageMask_Mask.

Backports commit 2d1847ec1ca47fe82f1d8122409cedffdd3925d5 from qemu
2018-03-04 01:27:51 -05:00
..
arm target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset 2018-03-04 01:20:57 -05:00
i386 tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
m68k tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
mips target-mips: apply CP0.PageMask before writing into TLB entry 2018-03-04 01:27:51 -05:00
sparc tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00