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4a540f88de
This patch implements read and write access rules for Mips floating point control and status register (FCR31). The change can be divided into following parts: - Add fields that will keep FCR31's R/W bitmask in procesor definitions and processor float_status structure. - Add appropriate value for FCR31's R/W bitmask for each supported processor. - Add function for setting snan_bit_is_one, and integrate it in appropriate places. - Modify handling of CTC1 (case 31) instruction to use FCR31's R/W bitmask. - Modify handling user mode executables for Mips, in relation to the bit EF_MIPS_NAN2008 from ELF header, that is in turn related to reading and writing to FCR31. - Modify gdb behavior in relation to FCR31. Backports commit 599bc5e89c46f95f86ccad0d747d041c89a28806 from qemu |
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| .. | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| dsp_helper.c | ||
| helper.c | ||
| helper.h | ||
| lmi_helper.c | ||
| Makefile.objs | ||
| mips-defs.h | ||
| msa_helper.c | ||
| op_helper.c | ||
| TODO | ||
| translate.c | ||
| translate_init.c | ||
| unicorn.c | ||
| unicorn.h | ||