unicorn/qemu/target
Peter Maydell 4abcf14b52
target/arm: Handle small regions in get_phys_addr_pmsav8()
Allow ARMv8M to handle small MPU and SAU region sizes, by making
get_phys_add_pmsav8() set the page size to the 1 if the MPU or
SAU region covers less than a TARGET_PAGE_SIZE.

We choose to use a size of 1 because it makes no difference to
the core code, and avoids having to track both the base and
limit for SAU and MPU and then convert into an artificially
restricted "page size" that the core code will then ignore.

Since the core TCG code can't handle execution from small
MPU regions, we strip the exec permission from them so that
any execution attempts will cause an MPU exception, rather
than allowing it to end up with a cpu_abort() in
get_page_addr_code().

(The previous code's intention was to make any small page be
treated as having no permissions, but unfortunately errors
in the implementation meant that it didn't behave that way.
It's possible that some binaries using small regions were
accidentally working with our old behaviour and won't now.)

We also retain an existing bug, where we ignored the possibility
that the SAU region might not cover the entire page, in the
case of executable regions. This is necessary because some
currently-working guest code images rely on being able to
execute from addresses which are covered by a page-sized
MPU region but a smaller SAU region. We can remove this
workaround if we ever support execution from small regions.

Backports commit 720424359917887c926a33d248131fbff84c9c28 from qemu
2018-07-03 00:55:37 -04:00
..
arm target/arm: Handle small regions in get_phys_addr_pmsav8() 2018-07-03 00:55:37 -04:00
i386 i386: Enable TOPOEXT feature on AMD EPYC CPU 2018-07-03 00:32:50 -04:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-15 11:40:18 -04:00
mips tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-07 11:56:32 -04:00
sparc tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-07 11:56:32 -04:00