Mike Nawrocki 4e482764e2 target/arm: Fix SCR RES1 handling ... The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them to 1 only when there is no support for AArch32 at EL1 or above. The reset value will be 0x30 only if the CPU is AArch64-only; if there is support for AArch32 at EL1 or above, it will be reset to 0. Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32 is supported at EL1 or above. Backports 10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5		2021-03-04 18:15:39 -05:00
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arm	target/arm: Fix SCR RES1 handling	2021-03-04 18:15:39 -05:00
i386	target/i386: Expose VMX entry/exit load pkrs control bits	2021-03-04 18:13:36 -05:00
m68k	cpu: move cc->transaction_failed to tcg_ops	2021-03-04 17:16:41 -05:00
mips	cpu: move do_unaligned_access to tcg_ops	2021-03-04 17:20:02 -05:00
riscv	cpu: move do_unaligned_access to tcg_ops	2021-03-04 17:20:02 -05:00
sparc	cpu: move do_unaligned_access to tcg_ops	2021-03-04 17:20:02 -05:00