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7d0d7338c2
Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d
84 lines
3.9 KiB
Plaintext
84 lines
3.9 KiB
Plaintext
#
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# RISC-V translation routines for the RV Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# This is concatenated with insn32.decode for risc64 targets.
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# Most of the fields and formats are there.
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%sh5 20:5
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@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
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# *** RV64I Base Instruction Set (in addition to RV32I) ***
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lwu ............ ..... 110 ..... 0000011 @i
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ld ............ ..... 011 ..... 0000011 @i
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sd ....... ..... ..... 011 ..... 0100011 @s
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addiw ............ ..... 000 ..... 0011011 @i
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slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
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srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
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sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
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addw 0000000 ..... ..... 000 ..... 0111011 @r
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subw 0100000 ..... ..... 000 ..... 0111011 @r
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sllw 0000000 ..... ..... 001 ..... 0111011 @r
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srlw 0000000 ..... ..... 101 ..... 0111011 @r
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sraw 0100000 ..... ..... 101 ..... 0111011 @r
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# *** RV64M Standard Extension (in addition to RV32M) ***
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mulw 0000001 ..... ..... 000 ..... 0111011 @r
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divw 0000001 ..... ..... 100 ..... 0111011 @r
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divuw 0000001 ..... ..... 101 ..... 0111011 @r
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remw 0000001 ..... ..... 110 ..... 0111011 @r
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remuw 0000001 ..... ..... 111 ..... 0111011 @r
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# *** RV64A Standard Extension (in addition to RV32A) ***
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lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
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sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
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amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
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amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
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amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
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amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
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amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
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amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
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amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
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amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
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amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
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#*** Vector AMO operations (in addition to Zvamo) ***
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vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
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vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
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# *** RV64F Standard Extension (in addition to RV32F) ***
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fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
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fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
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# *** RV64D Standard Extension (in addition to RV32D) ***
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fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
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fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
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fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
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fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
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