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b6f752970b
This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
14 lines
340 B
C
14 lines
340 B
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com> */
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#ifndef UC_QEMU_TARGET_RISCV_H
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#define UC_QEMU_TARGET_RISCV_H
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void riscv32_uc_init(struct uc_struct *uc);
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void riscv64_uc_init(struct uc_struct *uc);
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extern const int RISCV32_REGS_STORAGE_SIZE_riscv32;
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extern const int RISCV64_REGS_STORAGE_SIZE_riscv64;
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#endif
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