unicorn/qemu/target
Andrew Baumann 5250db33b5
arm: implement cache/shareability attribute bits for PAR registers
On a successful address translation instruction, PAR is supposed to
contain cacheability and shareability attributes determined by the
translation. We previously returned 0 for these bits (in line with the
general strategy of ignoring caches and memory attributes), but some
guest OSes may depend on them.

This patch collects the attribute bits in the page-table walk, and
updates PAR with the correct attributes for all LPAE translations.
Short descriptor formats still return 0 for these bits, as in the
prior implementation.

Backports commit 5b2d261d60caf9d988d91ca1e02392d6fc8ea104 from qemu
2018-03-05 11:35:28 -05:00
..
arm arm: implement cache/shareability attribute bits for PAR registers 2018-03-05 11:35:28 -05:00
i386 qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
m68k qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
mips qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
sparc qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00